M1A3P1000-1PQ208M Datasheet, PDF (145/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL Low Power Flash FPGAs
Timing Characteristics
Table 2-202 • RAM4K9
Military-Case Conditions: T_J = 125°C, Worst-Case VCC = 1.14 V for A3PE600L and A3PE3000L
Parameter
Description
–1 Std. Units
t_AS
t_AH
t_ENS
t_ENH
t_BKS
t_BKH
t_DS
t_DH
t_CKQ1
Address setup time
Address hold time
REN_B, WEN_B setup time
REN_B, WEN_B hold time
BLK_B setup time
BLK_B hold time
Input data (DI) setup time
Input data (DI) hold time
Clock High to new data valid on DO (output retained, WMODE = 0)
Clock High to new data valid on DO (flow-through, WMODE = 1)
0.35 0.41 ns
0.00 0.00 ns
0.20 0.23 ns
0.13 0.16 ns
0.32 0.38 ns
0.03 0.03 ns
0.25 0.30 ns
0.00 0.00 ns
3.26 3.84 ns
2.47 2.91 ns
t_CKQ2
t_C2CWWL
Clock High to new data valid on DO (pipelined)
1.24 1.46 ns
Address collision clk-to-clk delay for reliable write after write on same address – 0.25 0.30 ns
applicable to closing edge
t_C2CRWH
Address collision clk-to-clk delay for reliable read access after write on same 0.27 0.32 ns
address – applicable to opening edge
t_C2CRWH
Address collision clk-to-clk delay for reliable write access after read on same 0.37 0.44 ns
address – applicable to opening edge
t_RSTBQ
RESET_B Low to data out Low on DO (flow-through)
RESET_B Low to data out Low on DO (pipelined)
1.28 1.50 ns
1.28 1.50 ns
t_REMRSTB RESET_B removal
0.40 0.47 ns
t_RECRSTB RESET_B recovery
2.08 2.44 ns
t_MPWRSTB RESET_B minimum pulse width
0.66 0.76 ns
t_CYC
Clock cycle time
6.08 6.99 ns
F_MAX
Maximum frequency
164 143 MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.
Revision 3
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