M1A3P1000-1PQ208M Datasheet, PDF (47/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL Low Power Flash FPGAs
Table 2-36 • I/O Output Buffer Maximum Resistances ¹
Applicable to Advanced I/O Banks for A3P250 and A3P1000 Only
Standard
Drive Strength
R_{PU(LL-)D2OWN}
R_{P(UL)L3-UP}
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
100
300
4 mA
100
300
6 mA
50
150
8 mA
50
150
12 mA
25
75
16 mA
17
50
24 mA
11
33
3.3 V LVCMOS Wide Range
100 µA
Same as regular 3.3 V LVCMOS
2.5 V LVCMOS
2 mA
100
300
4 mA
100
300
6 mA
50
150
8 mA
50
150
12 mA
25
75
16 mA
17
50
24 mA
11
33
1.8 V LVCMOS
2 mA
100
200
4 mA
100
200
6 mA
50
100
8 mA
50
100
12 mA
25
50
16 mA
20
40
1.5 V LVCMOS
2 mA
200
224
4 mA
100
112
6 mA
67
75
8 mA
33
37
12 mA
33
37
3.3 V PCI/PCI-X
Per PCI/PCI-X specification
25
75
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend
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2. R_{(PULL-DOWN-MAX)} = (VOLspec) / I_OLspec
3. R_{(PULL-UP-MAX)} = (VCCImax – VOHspec) / I_OHspec
Revision 3
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