M1A3P1000-1PQ208M Datasheet, PDF (109/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL Low Power Flash FPGAs
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Clear
Data
Enable
CLK
CLR
DOUT
CC
D
Q
DFN1E1C1
Y
EE
Core
Array
Data_out ^FF
D
Q
DFN1E1C1
GG
E
BB
CLR
E
CLR
LL
EOUT
HH
AA
DD
Data Input I/O Register with
Active High Enable
Active High Clear
Positive-Edge Triggered
INBUF
JJ
D
Q
DFN1E1C1
KK
E
CLR
INBUF
CLKBUF
Data Output Register and
Enable Output Register with
Active High Enable
Active High Clear
Positive-Edge Triggered
Figure 2-30 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
Revision 3
2- 95