M1A3P1000-1PQ208M Datasheet, PDF (105/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL Low Power Flash FPGAs
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires
that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-28. The
building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVDS implementation because the output standard
specifications are different.
OUTBUF_LVPECL ^FPGA
Bourns Part Number: CAT16-PC4F12
P
100 
N
100 
Z₀ = 50 
P
187 W
100 
Z₀ = 50 
N
FPGA
+ ^INBUF_LVPECL
–
Figure 2-28 • LVPECL Circuit Diagram and Board-Level Implementation
Table 2-164 • Minimum and Maximum DC Input and Output Levels
DC Parameter
Description
Min. Max.
VCCI
Supply Voltage
3.0
VOL
Output Low Voltage
0.96 1.27
VOH
Output High Voltage
1.8 2.11
VIL, VIH
Input Low, Input High Voltages
0
3.3
V_ODIFF
V_OCM
V_ICM
V_IDIFF
Differential Output Voltage
Output Common-Mode Voltage
Input Common-Mode Voltage
Input Differential Voltage
0.625 0.97
1.762 1.98
1.01 2.57
300
Min. Max.
3.3
1.06 1.43
1.92 2.28
0
3.6
0.625 0.97
1.762 1.98
1.01 2.57
300
Min. Max.
3.6
1.30 1.57
2.13 2.41
0
3.9
0.625 0.97
1.762 1.98
1.01 2.57
300
Units
V
V
V
V
V
V
V
mV
Table 2-165 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
1.64
1.94
Cross point
Note: *Measuring point = V_trip. See Table 2-28 on page 2-27 for a complete table of trip points.
Revision 3
2- 91