M1A3P1000-1PQ208M Datasheet, PDF (121/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL Low Power Flash FPGAs
CLK
Data
CLR
Out_QF
Out_QR
1
2
3
4
5
t_DDRIREMCLR
t_DDRICLR2Q1
t_DDRICLR2Q2
t_DDRICLKQ1
2
3
t_DDRISUD
6
7
t_DDRIHD
8
9
t_DDRIRECCLR
4
6
t_DDRICLKQ2
5
7
Figure 2-35 • Input DDR Timing Diagram
Timing Characteristics
Table 2-181 • Input DDR Propagation Delays
Military-Case Conditions: T_J = 125°C, Worst-Case VCC = 1.14 V for A3PE600L and A3PE3000L
Parameter
Description
–1 Std. Units
t_DDRICLKQ1
Clock-to-Out Out_QR for Input DDR
0.38 0.45 ns
t_DDRICLKQ2
Clock-to-Out Out_QF for Input DDR
0.54 0.63 ns
t_DDRISUD1
Data Setup for Input DDR (fall)
0.39 0.46 ns
t_DDRISUD2
Data Setup for Input DDR (rise)
0.34 0.40 ns
t_DDRIHD1
Data Hold for Input DDR (fall)
0.00 0.00 ns
t_DDRIHD2
Data Hold for Input DDR (rise)
0.00 0.00 ns
t_DDRICLR2Q1
Asynchronous Clear-to-Out Out_QR for Input DDR
0.64 0.75 ns
t_DDRICLR2Q2
Asynchronous Clear-to-Out Out_QF for Input DDR
0.79 0.93 ns
t_DDRIREMCLR
Asynchronous Clear Removal Time for Input DDR
0.00 0.00 ns
t_DDRIRECCLR
Asynchronous Clear Recovery Time for Input DDR
0.31 0.36 ns
t_DDRIWCLR
Asynchronous Clear Minimum Pulse Width for Input DDR
0.19 0.22 ns
t_DDRICKMPWH Clock Minimum Pulse Width HIGH for Input DDR
0.31 0.36 ns
t_DDRICKMPWL
Clock Minimum Pulse Width LOW for Input DDR
0.28 0.32 ns
F_DDRIMAX
Maximum Frequency for Input DDR
TBD TBD MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.
Revision 3
2- 107