M1A3P1000-1PQ208M Datasheet, PDF (148/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL DC and Switching Characteristics
Table 2-205 • RAM512X18
Military-Case Conditions: T_J = 125°C, Worst-Case VCC = 1.14 V for A3PE600L and A3PE3000L
Parameter
Description
–1 Std. Units
t_AS
t_AH
t_ENS
t_ENH
t_DS
t_DH
t_CKQ1
t_CKQ2
t_C2CRWH
Address setup time
0.35 0.41 ns
Address hold time
0.00 0.00 ns
REN_B, WEN_B setup time
0.13 0.15 ns
REN_B, WEN_B hold time
0.08 0.09 ns
Input data (DI) setup time
0.25 0.30 ns
Input data (DI) hold time
0.00 0.00 ns
Clock High to new data valid on DO (output retained, WMODE = 0)
2.99 3.52 ns
Clock High to new data valid on DO (pipelined)
1.24 1.46 ns
Address collision clk-to-clk delay for reliable read access after write on same 0.25 0.29 ns
address – applicable to opening edge
t_C2CWRH
Address collision clk-to-clk delay for reliable write access after read on same 0.31 0.36 ns
address – applicable to opening edge
t_RSTBQ
RESET_B Low to data out Low on DO (flow through)
RESET_B Low to data out Low on DO (pipelined)
1.28 1.50 ns
1.28 1.50 ns
t_REMRSTB RESET_B removal
0.40 0.47 ns
t_RECRSTB RESET_B recovery
2.08 2.44 ns
t_MPWRSTB RESET_B minimum pulse width
0.66 0.76 ns
t_CYC
Clock cycle time
6.08 6.99 ns
F_MAX
Maximum frequency
164 143 MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.
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Revision 3