M1A3P1000-1PQ208M Datasheet, PDF (83/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL Low Power Flash FPGAs
1.2 V LVCMOS (JESD8-12A)
Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V
applications. It uses a 1.2 V input buffer and a push-pull output buffer.
Table 2-105 • Minimum and Maximum DC Input and Output Levels
Applicable to Pro I/O Banks for A3PE600L and A3PE3000L Only
1.2 V
LVCMOS¹
Drive
Min.
Strength V
VIL
Max.
V
VIH
Min.
V
Max.
V
VOL
Max.
V
VOH
Min.
V
I_OL I_OH I_OSH
Max.⁴
mA mA mA
I_OSL
Max.⁴
mA
I_IL2 I_IH3
µA⁵ µA⁵
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 TBD TBD 15 15
Notes:
1. Applicable to A3PE600L and A3PE3000L devices only.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
4. Currents are measured at 100°C junction temperature and maximum voltage.
5. Currents are measured at 125°C junction temperature.
6. Software default selection highlighted in gray.
Test Point
Datapath
5 pF
R=1k
Test Point
Enable Path
R to VCCI for t_LZ / t_ZL / t_ZLS
R to GND for t_HZ / t_ZH / t_ZHS
5 pF for t_ZH / t_ZHS / t_ZL / t_ZLS
5 pF for t_HZ / t_LZ
Figure 2-13 • AC Loading
Table 2-106 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
0
1.2
0.6
–
Note: *Measuring point = V_trip. See Table 2-28 on page 2-27 for a complete table of trip points.
C_LOAD (pF)
5
Revision 3
2- 69