M1A3P1000-1PQ208M Datasheet, PDF(104/212 Page) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

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M1A3P1000-1PQ208M Datasheet, PDF (104/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

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Military ProASIC3/EL DC and Switching Characteristics

B-LVDS/M-LVDS

Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to

high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain

any combination of drivers, receivers, and transceivers. Microsemi LVDS drivers provide the higher drive

current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series

terminations for better signal quality and to control voltage swing. Termination is also required at both

ends of the bus since the driver can be located anywhere on the bus. These configurations can be

implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations.

Multipoint designs using Microsemi LVDS macros can achieve up to 200 MHz with a maximum of 20

loads. A sample application is given in Figure 2-27. The input and output buffer delays are available in

the LVDS section in Table 2-159 on page 2-88.

Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required

differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: RS = 60 ï and

RT = 70 ï, given Z0 = 50 ï (2") and Zstub = 50 ï (~1.5").

Receiver

Transceiver

Driver

D EN

Receiver

RS RS

Zstub

Zstub ...

RT Z0

Transceiver

RS RS

BIBUF_LVDS

Figure 2-27 â¢ B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers

2-90

Revision 3

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