M1A3P1000-1PQ208M Datasheet, PDF (42/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL DC and Switching Characteristics
1.2 V Core Operating Voltage
Table 2-30 •
Summary of I/O Timing Characteristics—Software Default Settings
–1 Speed Grade, Military-Case Conditions: T_J = 125°C, Worst Case VCC = 1.14 V, Worst Case
VCCI
Applicable to Pro I/Os for A3PE600L and A3PE3000L Only
Standard
3.3 V LVTTL / 12 mA 12 mA High 5 – 0.68 2.09 0.05 1.49 2.03 0.44 2.12 1.56 2.76 3.06 3.99 3.43
3.3 V LVCMOS
3.3 V LVCMOS 100 µA 12 mA High 5 – 0.68 3.01 0.04 1.86 2.69 0.44 3.01 2.22 4.03 4.42 4.89 4.09
Wide Range³
2.5 V LVCMOS 12 mA 12 mA High 5 – 0.68 2.12 0.04 1.73 2.17 0.44 2.15 1.74 2.84 2.95 4.03 3.62
1.8 V LVCMOS 12 mA 12 mA High 5 – 0.68 2.36 0.05 1.70 2.40 0.44 2.40 1.94 3.16 3.58 4.27 3.81
1.5 V LVCMOS 12 mA 12 mA High 5 – 0.68 2.71 0.04 1.86 2.61 0.44 2.76 2.24 3.34 3.69 4.63 4.12
1.2 V LVCMOS 2 mA 2 mA High 5 – 0.68 4.39 0.04 2.25 3.19 0.44 4.24 3.74 4.34 4.09 6.11 5.61
1.2 V LVCOMS 100 µA 2 mA High 5 – 0.68 4.39 0.04 2.25 3.19 0.44 4.24 3.74 4.34 4.09 6.11 5.61
Wide Range⁴
3.3 V PCI
Per PCI – High 10 25⁵ 0.68 2.37 0.04 2.31 3.13 0.44 2.40 1.68 2.77 3.06 4.28 3.56
spec
3.3 V PCI-X Per PCI-X – High 10 25⁵ 0.68 2.37 0.04 2.31 3.13 0.44 2.40 1.68 2.77 3.06 4.28 3.56
spec
3.3 V GTL
20 mA⁶ 20 mA⁶ High 10 25 0.68 1.75 0.05 1.99 – 0.44 1.71 1.75 – – 3.59 3.62
2.5 V GTL
20 mA⁶ 20 mA⁶ High 10 25 0.68 1.79 0.05 1.93 – 0.44 1.82 1.79 – – 3.70 3.67
3.3 V GTL+
35 mA 35 mA High 10 25 0.68 1.74 0.05 1.99 – 0.44 1.76 1.73 – – 3.64 3.61
2.5 V GTL+
33 mA 33 mA High 10 25 0.68 1.86 0.05 1.93 – 0.44 1.89 1.77 – – 3.77 3.64
HSTL (I)
HSTL (II)
8 mA 8 mA High 20 25 0.68 2.68 0.05 2.34 – 0.44 2.73 2.65 –
15 mA⁶ 15 mA⁶ High 20 50 0.68 2.55 0.05 2.34 – 0.44 2.59 2.28 –
– 4.60 4.52
– 4.47 4.16
SSTL2 (I)
15 mA 15 mA High 30 25 0.68 1.80 0.05 1.78 – 0.44 1.82 1.55 – – 1.82 1.55
SSTL2 (II)
15 mA 15 mA High 30 50 0.68 1.83 0.05 1.78 – 0.44 1.86 1.49 – – 1.86 1.49
SSTL3 (I)
14 mA 14 mA High 30 25 0.68 1.95 0.05 1.71 – 0.44 1.98 1.55 – – 1.98 1.55
SSTL3 (II)
21 mA 21 mA High 30 50 0.68 1.75 0.05 1.71 – 0.44 1.77 1.41 – – 1.77 1.41
LVDS
24 mA
– High – – 0.68 1.59 0.05 2.11 – – – – – – – –
LVPECL
24 mA
– High – – 0.68 1.51 0.05 1.84 – – – – – – – –
Notes:
1. Note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range are applicable to 100 µA drive strength only. The configuration
will not operate at the equivalent software default drive strength. These values are for normal ranges only.
2. Output delays provided in this table were extracted with an output load indicated in the Capacitive Load column. For a
specific output load, refer to Designer software.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
4. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.
5. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-15 on page 2-73 for
connectivity. This resistor is not required during normal operation.
6. Output drive strength is below JEDEC specification.
7. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.
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