M1A3P1000-1PQ208M Datasheet, PDF (17/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL Low Power Flash FPGAs
Tj (°C)
70
85
100
105
110
115
120
125
130
135
140
145
150
HTR
Lifetime
(yrs)
102.7
43.8
20.0
15.6
12.3
9.7
7.7
6.2
5.0
4.0
3.3
2.7
2.2
110
100
90
80
70
60
50
40
30
20
10
0
70 85 100 105 110 115 120 125 130 135 140 145 150
Temperature (ºC)
Note: HTR time is the period during which you would not expect a verify failure due to flash cell leakage.
Figure 2-1 • High-Temperature Data Retention (HTR)
Table 2-3 • Overshoot and Undershoot Limits¹
VCCI and VMV
Average VCCI–GND Overshoot or Undershoot
Duration as a Percentage of Clock Cycle²
Maximum Overshoot/
Undershoot (125°C)²
2.7 V or less
10%
0.72 V
5%
0.82 V
3V
10%
0.72 V
5%
0.82 V
3.3 V
10%
0.69 V
5%
0.79 V
3.6 V
10%
N/A
5%
N/A
Notes:
1. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the
maximum overshoot/undershoot has to be reduced by 0.15 V.
2. This table does not provide PCI overshoot/undershoot limits.
Revision 3
2-3