M1A3P1000-1PQ208M Datasheet, PDF (41/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL Low Power Flash FPGAs
Summary of I/O Timing Characteristics – Default I/O Software Settings
Table 2-28 • Summary of AC Measuring Points
Standard
Input/Output
Input Reference Board Termination
Supply Voltage Voltage (VREF_TYP) Voltage (VTT_REF)
3.3 V LVTTL /
3.30 V
–
–
3.3 V LVCMOS
3.3 V LVCMOS Wide Range
3.30 V
–
–
2.5 V LVCMOS
2.50 V
–
–
1.8 V LVCMOS
2.50 V
–
–
1.5 V LVCMOS
1.80 V
–
–
1.2 V LVCMOS*
1.50 V
–
–
1.2 V LVCMOS Wide Range*
1.20 V
–
–
3.3 V PCI
1.20 V
–
–
3.30 V
–
–
3.3 V PCI-X
3.30 V
–
–
3.30 V
–
–
3.3 V GTL
2.50 V
0.8 V
1.2 V
2.5 V GTL
3.30 V
0.8 V
1.2 V
3.3 V GTL+
2.50 V
1.0 V
1.5 V
2.5 V GTL+
1.50 V
1.0 V
1.5 V
HSTL (I)
1.50 V
0.75 V
0.75 V
HSTL (II)
3.30 V
0.75 V
0.75 V
SSTL2 (I)
3.30 V
1.25 V
1.25 V
SSTL2 (II)
2.50 V
1.25 V
1.25 V
SSTL3 (I)
2.50 V
1.5 V
1.485 V
SSTL3 (II)
2.50 V
1.5 V
1.485 V
LVDS
3.30 V
–
–
LVPECL
–
–
Note: *Applicable to A3PE600L and A3PE3000L devices operating at 1.2 V core regions only.
Measuring Trip
Point (Vtrip)
1.4 V
1.4 V
1.2 V
0.90 V
0.75 V
0.6 V
0.6 V
0.285 * VCCI (RR)
0.615 * VCCI (FF))
0.285 * VCCI (RR)
0.615 * VCCI (FF)
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
Cross point
Cross point
Table 2-29 • I/O AC Parameter Definitions
Parameter
Parameter Definition
t_DP
t_PY
t_DOUT
t_EOUT
t_DIN
t_HZ
t_ZH
t_LZ
t_ZL
t_ZHS
t_ZLS
Data to Pad delay through the Output Buffer
Pad to Data delay through the Input Buffer
Data to Output Buffer delay through the I/O interface
Enable to Output Buffer Tristate Control delay through the I/O interface
Input Buffer to Data delay through the I/O interface
Enable to Pad delay through the Output Buffer—High to Z
Enable to Pad delay through the Output Buffer—Z to High
Enable to Pad delay through the Output Buffer—Low to Z
Enable to Pad delay through the Output Buffer—Z to Low
Enable to Pad delay through the Output Buffer with delayed enable—Z to High
Enable to Pad delay through the Output Buffer with delayed enable—Z to Low
Revision 3
2- 27