M1A3P1000-1PQ208M Datasheet, PDF (132/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL DC and Switching Characteristics
Timing Characteristics
Table 2-191 • Register Delays
Military-Case Conditions: T_J = 125°C, Worst-Case VCC = 1.14 V for A3PE600L and A3PE3000L
Parameter
Description
–1 Std. Units
t_CLKQ
Clock-to-Q of the Core Register
0.76 0.90 ns
t_SUD
Data Setup Time for the Core Register
0.59 0.70 ns
t_HD
Data Hold Time for the Core Register
0.00 0.00 ns
t_SUE
Enable Setup Time for the Core Register
0.63 0.74 ns
t_HE
Enable Hold Time for the Core Register
0.00 0.00 ns
t_CLR2Q
Asynchronous Clear-to-Q of the Core Register
0.55 0.65 ns
t_PRE2Q
Asynchronous Preset-to-Q of the Core Register
0.55 0.65 ns
t_REMCLR
Asynchronous Clear Removal Time for the Core Register
0.00 0.00 ns
t_RECCLR
Asynchronous Clear Recovery Time for the Core Register
0.31 0.36 ns
t_REMPRE
Asynchronous Preset Removal Time for the Core Register
0.00 0.00 ns
t_RECPRE
Asynchronous Preset Recovery Time for the Core Register
0.31 0.36 ns
t_WCLR
Asynchronous Clear Minimum Pulse Width for the Core Register
0.30 0.34 ns
t_WPRE
Asynchronous Preset Minimum Pulse Width for the Core Register
0.30 0.34 ns
t_CKMPWH
Clock Minimum Pulse Width HIGH for the Core Register
0.56 0.64 ns
t_CKMPWL
Clock Minimum Pulse Width LOW for the Core Register
0.56 0.64 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.
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Revision 3