M1A3P1000-1PQ208M Datasheet, PDF(32/212 Page) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

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M1A3P1000-1PQ208M Datasheet, PDF (32/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

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Military ProASIC3/EL DC and Switching Characteristics

Combinatorial Cells ContributionâPC-CELL

PC-CELL = NC-CELL* ï¡1 / 2 * PAC7 * FCLK

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

ï¡1 is the toggle rate of VersaTile outputsâguidelines are provided in Table 2-22 on

page 2-19.

FCLK is the global clock signal frequency.

Routing Net ContributionâPNET

PNET = (NS-CELL + NC-CELL) * ï¡1 / 2 * PAC8 * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design.

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

ï¡1 is the toggle rate of VersaTile outputsâguidelines are provided in Table 2-22 on

page 2-19.

FCLK is the global clock signal frequency.

I/O Input Buffer ContributionâPINPUTS

PINPUTS = NINPUTS * ï¡2 / 2 * PAC9 * FCLK

NINPUTS is the number of I/O input buffers used in the design.

ï¡2 is the I/O buffer toggle rateâguidelines are provided in Table 2-22 on page 2-19.

FCLK is the global clock signal frequency.

I/O Output Buffer ContributionâPOUTPUTS

POUTPUTS = NOUTPUTS * ï¡2 / 2 * ï¢1 * PAC10 * FCLK

NOUTPUTS is the number of I/O output buffers used in the design.

ï¡2 is the I/O buffer toggle rateâguidelines are provided in Table 2-22 on page 2-19.

ï¢1 is the I/O buffer enable rateâguidelines are provided in Table 2-23 on page 2-19.

FCLK is the global clock signal frequency.

RAM ContributionâPMEMORY

ï¢ ï¢ PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3

NBLOCKS is the number of RAM blocks used in the design.

FREAD-CLOCK is the memory read clock frequency.

ï¢2 is the RAM enable rate for read operations.

FWRITE-CLOCK is the memory write clock frequency.

ï¢3 is the RAM enable rate for write operationsâguidelines are provided in Table 2-23 on

page 2-19.

PLL ContributionâPPLL

PPLL = PDC4 + PAC13 * FCLKOUT

FCLKOUT is the output clock frequency.1

1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding

contribution (PAC13* FCLKOUT product) to the total PLL contribution.

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Revision 3

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