82091AA Datasheet, PDF (98/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
Table 20 Serial Port Register Summary
Receiver Transmitter
Bit
Buffer
Holding
Register Register
Interrupt
Enable
Register
Interrupt
Identification
Register
FIFO Control
Register
Line Control
Register
0 Data Bit 0 Data Bit 0
Enable Received 0 if Interrupt
Data Available Pending
Interrupt
FIFO Enable Word Length
Select Bit 0
1 Data Bit 1 Data Bit 1
Enable XMTR
Holding Register
Empty Interrupt
Interrupt ID Bit
RCVR FIFO
Reset
Word Length
Select Bit 1
2 Data Bit 2 Data Bit 2
Enable RCVR
Line Status
Interrupt
Interrupt ID Bit XMIT FIFO
Reset
Number of Stop
Bits
3 Data Bit 3 Data Bit 3
Enable Modem Interrupt ID Bit DMA Mode
Status Interrupt (Non-FIFO^e0) Select
Parity Enable
4 Data Bit 4 Data Bit 4
0
0
Reserved
Event Parity Select
5 Data Bit 5 Data Bit 5
0
0
Reserved
Stick Parity
6 Data Bit 6 Data Bit 6
0
FIFOs Enabled RCVR Trigger Set Break
(Non-FIFO^e0) (LSB)
7 Data Bit 7 Data Bit 7
0
FIFOs Enabled RCVR Trigger Divisor Latch
(Non-FIFO^e0) (MSB)
Access Bit (DLAB)
Table 20 Serial Port Register Summary (Continued)
Bit
Modem
Control
Register
Line Status
Register
Modem
Status
Register
ScratchPad Divisor Latch Divisor Latch
Register
- MSB
- LSB
0 Data Terminal Data Ready
Delta Clear to
Bit 0
Bit 0
Bit 8
Ready (DTR) (DR)
Send
1 Request to Overrun Error Delta Data Set
Bit 1
Bit 1
Bit 9
Send (RTS) (OE)
Ready
2 Out 1 Bit
Parity Error
(PE)
Trailing Edge
Ring Indicator
Bit 2
Bit 2
Bit 10
3 IRQ Enable
Framing Error
(FE)
Delta Data
Carrier Detect
Bit 3
Bit 3
Bit 11
4 Loop
Break Interrupt Clear to Send
(BI)
(CTS)
Bit 4
Bit 4
Bit 12
5
0
Transmitter
Data Set
Bit 5
Holding Register Ready (DSR)
(THRE)
Bit 5
Bit 13
6
0
Transmitter
Ring Indicator
Bit 6
Empty (TEMT) (RI)
Bit 6
Bit 14
7
0
Error in RCVR Data Carrier
Bit 7
FIFO
Detect (DCD)
Bit 7
Bit 15
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