82091AA Datasheet, PDF (110/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
Figure 54 Line Status Register
290486 – 54
Bit
Description
7 FIFO ERROR STATUS (FIFOE) In the non-FIFO Mode this is a 0 In the FIFO Mode FIFOE is set to
1 when there is at least one parity error framing error or break indication in the FIFO FIFOE is set
to 0 when the CPU reads the LSR if there are no subsequent errors in the FIFO
6 TRANSMITTER EMPTY STATUS (TEMT) This bit is the Transmitter Empty (TEMT) indicator When
the Transmitter Holding Register (THR) and the Transmitter Shift Register (TSR) are both empty the
82091AA sets TEMT to a 1 When either the THR or TSR contains a data character TEMT is set to
a 0 The default is 0 In FIFO mode this bit is set to 1 when the transmitter FIFO and the shift
register are both empty
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