82091AA Datasheet, PDF (97/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
7 0 SERIAL PORT
The two 82091AA serial ports are identical This
section describes the serial port registers and FIFO
operations
7 1 Register Description
The register descriptions in this section apply to both
serial port A and serial port B and provide a com-
plete operational description of the serial ports Ta-
ble 19 shows the I O address assignments for the
serial port registers The individual register descrip-
tions follow in the order that they appear in the table
Note that serial port interrupt assignments (IRQ3 or
IRQ4) and the base address assignments are made
by 82091AA configuration as described in Section
4 0 AIP Configuration
All registers are accessed as byte quantities The
base address is determined by hardware configura-
tion at powerup (or a hard reset) or via software con-
figuration by programming the 82091AA configura-
tion registers as described in Section 4 0 AIP Con-
figuration Note that access to certain serial port reg-
isters requires prior programming of the DLAB bit in
the Line Control Register (LCR)
During a hard reset (RSTDRV asserted) the
82091AA registers are set to pre-determined de-
fault states The default values are indicated in the
individual register descriptions Reserved bits in the
82091AA’s serial port registers must be pro-
grammed to 0 when writing the register and these
bits are 0 when read The following bit notation is
used for default settings
X Default bit position value is determined by
conditions on an 82091AA signal pin
The following nomenclature is used for serial port
register access attributes
RO Read Only Note that for all registers with
read only attributes writes to the I O address
access a different register
WO Write Only Note that for all registers with
write only attributes reads to the I O address
access a different register
R W Read Write A register with this attribute can
be read and written Note that some read
write registers contain bits that are read only
Table 19 Serial Port Registers
Register Address
Access (AEN^e0)
Abbreviation
Register Name
Access
Base ^a
DLAB
0h
0
THR
Transmit Holding Register
WO
0h
0
RBR
Receiver Buffer Register
RO
0h
1
DLL
Divisor Latch LSB
RW
1h
1
DLM
Divisor Latch MSB
RW
1h
0
IER
Interrupt Enable Register
RW
2h
IIR
Interrupt Identification Register
RO
2h
FCR
FIFO Control Register
WO
3h
LCR
Line Control Register
RW
4h
MCR
Modem Control Register
RW
5h
LSR
Line Status Register
RW
6h
MSR
Modem Status Register
RW
7h
SCR
Scratch Pad Register
RW
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