82091AA Datasheet, PDF (10/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
Floppy Disk Controller
The 82091AA’s enhanced floppy disk controller
(FDC) incorporates several new features allowing for
easy implementation in both the portable and desk-
top markets It provides a low cost small form factor
solution targeted for 5 0V and 3 3V platforms The
FDC supports up to four drives
The 82091AA’s FDC implements these new features
while remaining functionally compatible with 82078
82077SL 82077AA 8272A floppy disk controllers
Together with a 24-MHz crystal a resistor package
and a device chip select these devices allow for the
most integrated solution available The integrated
analog PLL data separator has better performance
than most board level discrete PLL implementations
and can be operated at 1 Mbps 500 Kbps
300 Kbps 250 Kbps A 16-byte FIFO substantially
improves system performance and is ideal for multi-
master systems (e g EISA)
Serial Ports
The 82091AA contains two independent serial ports
that provide asynchronous communications that are
equivalent to two 16550 UARTs The serial ports
have identical circuitry and provide the serial com-
munication interface to a peripheral device or mo-
dem via Serial Port A and Serial Port B Each serial
port can be configured for one of eight address as-
signments The standard PC AT compatible logical
address assignments for COM1 COM2 COM3 and
COM4 are supported
The serial ports perform serial-to-parallel conversion
on data characters received from a peripheral de-
vice or modem and parallel-to-serial conversion on
data characters received from the host The serial
ports can operate in either FIFO mode or non-FIFO
mode In FIFO mode a 16-byte transmit FIFO holds
data from the host to be transmitted on the serial
link and a 16-byte receive FIFO that buffers data
from the serial link until read by the host
The serial ports contain programmable baud rate
generators that divide the internal reference clock
by divisors of 1 to (2^{16 b} 1) and produce a 16x
clock for driving the transmitter and receiver logic
The internal reference clock can be programmed to
support MIDI The serial ports have complete mo-
dem-control capability and a prioritized interrupt sys-
tem
Parallel Port
The 82091AA provides a multi-function parallel port
that transfers information between the host and pe-
ripheral device (e g printer) The parallel port inter-
face contains nine control status lines and an 8-bit
data bus The standard PC AT compatible logical
address assignments for LPT1 LPT2 and LPT3 are
supported The parallel port can be configured for
one of four modes and supports the following IEEE
Standard 1284 parallel interface protocol standards
Parallel Port
Mode
ISA-Compatible Mode
PS 2-Compatible Mode
EPP Mode
ECP Mode
Parallel Interface
Protocol
Compatibility Nibble
Byte
EPP
ECP
For ISA-Compatible and PS 2-Compatible modes
software controls the handshake signals on the par-
allel port interface to transfer data between the host
and peripheral device Status and Control registers
permit software to monitor the state of the peripheral
device and generate handshake sequences
The EPP parallel port interface protocol increases
throughput by specifying an automatic handshake
sequence In EPP mode the 82091AA parallel port
automatically generates this handshake sequence in
hardware to transfer data between the host and
peripheral device
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