82091AA Datasheet, PDF (41/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
Figure 12 Parallel Port Power Management and Status Register
290486 – 12
Bit
Description
7 6 RESERVED
5 PARALLEL PORT FIFO ERROR STATUS (PFERR) When PFERR^e1 a FIFO underrun or overrun
condition has occurred This bit is read only Setting PRESET to 1 clears this bit to 0
4 RESERVED
3 PARALLEL PORT AUTO POWERDOWN ENABLE (PAPDN) When PAPDN^e1 the parallel port
can enter auto powerdown if the required auto powerdown conditions are met When PAPDN^e0
auto powerdown is disabled
2 PARALLEL PORT RESET (PRESET) When PRESET is set to 1 the parallel port is reset (i e all
programming and current state information is lost) This is the same state the module would be in
after a hard reset (RSTDRV asserted) to the 82091AA When resetting the parallel port via this
configuration bit the software must toggle this bit and ensure the reset active time (PRESET^e1) of
1 13 ms minimum is met
1 PARALLEL PORT IDLE STATUS (PIDLE) This bit reflects the idle state of the parallel port When
the parallel port is in an idle state (i e when the same conditions are met that apply to entering auto
powerdown) the 82091AA sets this bit to 1 The parallel port idle state is defined as the FIFO empty
and no activity on the parallel port interface This bit is read only
0 PARALLEL PORT DIRECT POWERDOWN (PDPDN) When PDPDN is set to 1 the parallel port
enters direct powerdown When PDPDN is set to 0 the parallel port is not in direct powerdown Note
that a parallel port module reset (PRESET bit in this register) also brings the parallel port out of the
direct powerdown state
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