82091AA Datasheet, PDF (128/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
8 2 Reset
There are four sources of FDC reset a hard reset
via the RSTDRV signal and three software resets
(via the FCFG2 DOR and DSR Registers) At the
end of the reset the FDC comes out of the power-
down state Note that the DOR reset condition re-
mains in effect until software programs the DORRST
bit to 1 in the DOR All operations are terminated
and the FDC enters an idle state Invoking a reset
while a disk write activity is in progress will corrupt
the data and CRC On exiting the reset state various
internal registers are cleared and the FDC waits for
a new command Drive polling will start unless dis-
abled by a new CONFIGURE Command
8 2 1 HARD RESET AND CONFIGURATION
REGISTER RESET
A hard reset (asserting RSTDRV) and a software re-
set through the FCFG2 Registers have the same af-
fect on the FDC These resets clear all FDC regis-
ters except those programmed by the SPECIFY
command The DOR reset bit is enabled and must
be set to 0 by the host to exit the reset state
8 2 2 DOR RESET vs DSR RESET
The DOR and DSR resets are functionally the same
The DSR reset is included to maintain 82072 com-
patibility Both reset the 8272 core which affects
drive status information The FIFO circuits are also
reset if the LOCK bit is a 0 (see definition of the
LOCK bit) The DSR reset is self-clearing (exits the
reset state automatically) while the DOR reset re-
mains in the reset state until software writes the
DOR reset bit to 0 DOR reset has precedence over
the DSR reset The DOR reset is set automatically
when a hard reset or configuration reset occurs
Software must set the DOR reset bit to 0 to exit the
reset state
The AC Specifications gives the minimum amount of
time that the DOR reset must be held active This
amount of time that the DOR reset must be held
active is dependent upon the data rate FDC re-
quires that the DOR reset bit must be held active for
at least 0 5 ms at 250 Kbps This is less than a typi-
cal ISA I O cycle time
8 3 DMA Transfers
DMA transfers are enabled with the SPECIFY Com-
mand When enabled The FDC initiates DMA trans-
fers by asserting the FDDREQ signal during a data
transfer command The FIFO is enabled directly by
asserting FDDACK and addresses need not be
valid
8 4 Controller Phases
The FDC handles commands in three phases com-
mand execution and result Each phase is de-
scribed in the following sections When not process-
ing a command the FDC can be in the idle drive
polling or powerdown state This section describes
the command execute and result phases
8 4 1 COMMAND PHASE
After a reset the FDC enters the command phase
and is ready to accept a command from the host
For each of the commands a defined set of com-
mand code bytes and parameter bytes must be writ-
ten to the FDC (as described in Section 8 8 Com-
mand Set Description) before the command phase
is complete These bytes of data must be trans-
ferred in the order described
Before writing to the FDC the host must examine
the RQM and DIO bits of the Main Status Register
RQM must be 1 and DIO must be 0 before com-
mand bytes may be written The FDC sets RQM to 0
after each write cycle and keeps the bit at 0 until the
received byte is processed After processing the
byte the FDC sets RQM to 1 again to request the
next parameter byte of the command unless an ille-
gal command condition is detected After the last
parameter byte is received RQM remains 0 and the
FDC automatically enters the next phase (execution
or result phase) as defined by the command defini-
tion
The FIFO is disabled during the command phase to
retain compatibility with the 8272A and to provide
for the proper handling of the Invalid Command con-
dition
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