82091AA Datasheet, PDF (95/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
Test Mode (ECR 7 5 ^e110) and Configuration
Mode (ECR7 5 ^e111)
The test mode can be used to check the FIFO read
and write interrupt thresholds as described in Sec-
tion 6 1 3 7 TFIFO ECP Test FIFO Register Note
that for the 82091AA parallel port the read and write
FIFO interrupt thresholds are the same The FIFO
threshold is set by programming the PCFG1 Regis-
ter in the 82091AA configuration space The config-
uration mode is used to access the ECPCFGA and
ECPCFGB Registers This mode must first be set
before the ECPCFGA and ECPCFGB Registers can
be accessed
6 2 3 1 FIFO Operations
The parallel port FIFO is used for ECP transfers
(ECR 7 5 ^e011) ISA-Compatible FIFO transfers
(ECR 7 5 ^e010) and Test mode (ECR 7 5 ^e110)
Either DMA or programmed I O can be used for
transfers between the host and the parallel port
The FIFO threshold value is selected via the
82091AA configuration registers (PCFG1 Register)
The threshold is set to either 1 (forward) 15 (re-
verse) or 8 in both directions A threshold setting of
1 (forward) 15 (reverse) results in longer periods of
time between service request but requires faster
servicing of both read and write requests A thresh-
old setting of 8 results in more service requests but
tolerates slower servicing of the requests
In modes 010 and 011 an internal temporary hold-
ing register is used in conjunction with the 16-byte
FIFO to provide 17 bytes of storage for both forward
and reverse transfers Thus in the forward direction
if the peripheral asserts the BUSY signal during the
filling of the FIFO the host needs to write 17 bytes
before the FIFO full flag in the ECR is set to 1 In
Test mode (110) only the 16-byte FIFO is used and
the temporary holding register is not used
The FIFO is reset by a hard reset (RSTDRV assert-
ed) or whenever the parallel port is placed in ISA-
Compatible or PS 2-Compatible modes Note that
the FIFO threshold can only be changed when the
parallel port is in ISA-Compatible or PS 2-Compati-
ble mode
6 2 3 2 DMA Transfers
The 82091AA contains parallel port DMA request
(PPDREQ) and acknowledge (PPDACK ) signals to
communicate with a standard PC DMA controller
Before initiating a DMA transfer the direction bit in
the PCON Register must be set to the proper direc-
tion To initiate DMA transfers software sets the
DMAEN bit to 1 and the SERVICEINTR bit to 0 in the
ECR The PPDREQ and PPDACK signals will then
be used to fill (forward direction) or empty (reverse
direction) the FIFO When the DMA controller reach-
es terminal count and asserts the TC signal an inter-
rupt is generated and the SERVICEINTR bit is set to
1 To reset the TC interrupt software can either
switch the mode to 000 or 001 or write the DMAEN
bit to 0
In DMA mode if 32 consecutive reads or writes are
performed to the FIFO and PPDREQ is still asserted
the 82091AA negates PPDREQ for the length of the
last PPDACK command pulse to force an arbitra-
tion cycle on the ISA Bus
6 2 3 3 Reset FIFO and DMA Terminal Count
Interrupt
The following operations are used to reset the paral-
lel port FIFO and TC interrupt
Function
FIFO
FIFO Error
TC Interrupt
Reset Operations
-Changing to modes 000 or 001
-Hard reset
-Changing to modes 000 or 001
-Hard reset
-Changing to modes 000 or 001
-Setting DMAEN to 0 in ECR
-Hard reset
6 2 3 4 Programmed I O Transfers
Programmed I O (non-DMA) can also be used for
transfers between the host and the parallel port
FIFO Software can determine the read write FIFO
thresholds and the FIFO depth by accessing the
FIFO in Test mode To use programmed I O trans-
fers software sets the direction bit in the PCON Reg-
ister to the desired direction and sets the DMAEN bit
to 0 and the SERVICEINTR bit to 0 in the ECR The
parallel port requests programmed I O transfers
from the host by asserting IRQ5 IRQ7
In the reverse direction an interrupt occurs when
SERVICEINTR^e0 either 8 or 15 bytes (depending
on threshold setting) are in the FIFO IRQ5 IRQ7
can be used in an interrupt-driven system The host
must respond to the interrupt request by reading
data from the FIFO
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