82091AA Datasheet, PDF (40/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
Bit
Description
2 1 PARALLEL PORT ADDRESS SELECT (PADS) This field selects the address for the parallel port
as follows
Bits 2 1
00
01
10
11
Address
378 – 37F
278 – 27F
3BC – 3BE
Reserved
Parallel Port Hardware Mode
All
All
All except EPP
None do not write
This field can be configured by strapping options at powerup for HWB and HWE modes only For all
other hardware configuration modes (SWMB and SWAI) the default is 00 (378h – 37Fh) Note that
the SWMB and SWAI default settings for PIRQSEL (bit 3) and PADS (bits 2 1 ) do not match a
standard PC AT combination for address assignment and interrupt setting However for SWMB
and SWAI the parallel port defaults to a disabled condition and this register must be programmed to
enable the parallel port (i e bit 0 set to 1) At this time the selections for interrupt and address
assignments should be made
0 PARALLEL PORT ENABLE (PEN) When PEN^e0 the parallel port is disabled When PEN^e1 the
parallel port is enabled This bit can be configured by hardware strapping options at powerup for
HWB and HWE modes only For all other hardware configuration modes (SWMB and SWAI) the
default is 0 (disabled) Note that when the parallel port is disabled IRQ 7 5 and PPDREQ are tri-
stated
4 1 9 PCFG2 PARALLEL PORT POWER MANAGEMENT AND STATUS REGISTER
Index Address
Default Value
Attribute
Size
21h
RR0R 0000
Read Write
8 bits
This register enables disables parallel port auto powerdown and can place the parallel port into a powerdown
mode directly The register also provides parallel port idle status resets the parallel port and reports FIFO
underrun or overrun errors
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