82091AA Datasheet, PDF (109/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
Bit
Description
7 5 RESERVED
4 LOOPBACK MODE ENABLE (LME) LME provides a local loopback feature for diagnostic testing of
the serial port module When LME^e1 the following occurs
1 The transmitter Serial Output (SOUT) is set to the Marking (logic 1) state
2 The receiver Serial Input (SIN) is disconnected
3 The output of the Transmitter Shift Register is ‘‘looped back’’(connected) to the Receiver Shift
Register
4 The four modem control inputs (DSR CTS RI and DCD ) are disconnected
5 The DTRC RTSC OUT1C IE bits in the MCR are internally connected to DSRS CTSS RIS and
DCDS in MSR respectively
6 The modem control output pins are forced to their high (inactive) state
7 Data that is transmitted is immediately received
This feature allows the CPU to verify the transmit and received data paths of the serial port In the
loopback mode the receiver and transmitter interrupts are fully operational The modem status
interrupts are fully operational The modem status interrupts are also operational but the interrupt
sources are the lower four bits of MCR instead of the four modem control inputs Writing a 1 to any
of these 4 MCR bits (bits 3 0 ) causes an interrupt In Loopback Mode the interrupts are still
controlled by the Interrupt Enable Register The IRQ3 and IRQ4 signal pins are tri-stated in the
loopback mode
3 INTERRUPT ENABLE (IE) When IE^e1 the associated interrupt is enabled (either IRQ3 or IRQ4 as
selected via the associated serial port configuration register - A or B) In Local Loopback Mode this
bit controls bit 7 of the Modem Status Register
2 OUT1 BIT CONTROL (OUT1C) This bit is the OUT1 bit It does not have an output pin associated
with it It can be written to and read by the CPU In Local Loopback Mode this bit controls bit 6 of the
Modem Status Register
1 REQUEST TO SEND CONTROL (RTS) This bit controls the Request to Send (RTS ) output
When RTSC^e1 the RTS output is asserted When RTSC^e0 the RTS output is negated In
Local Loopback Mode this bit controls bit 4 of the Modem Status Register
0 DATA TERMINAL READY CONTROL (DTRC) This bit controls the Data Terminal Ready (DTR )
output When DTRC^e1 the DTR output is asserted When DTRC^e0 the DTR output is
negated In Local Loopback Mode this bit controls bit 5 of the Modem Status Register
NOTE
The DTR and RTS outputs of the serial port may be applied to an EIA inverting line driver (such
as the DS1488) to obtain the proper polarity input at the modem or data set
7 1 9 LSR(A B) LINE STATUS REGISTER
I O Address
Default Value
Attribute
Size
Base ^a5h
60h
Read Write
8 bits
This 8-bit register provides data transfer status information to the CPU Note that the Line Status Register is
intended for read operations only Writing to this register is not recommended and could result in unintended
operations For this reason the figure shows these bits as RO (read only)
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