82091AA Datasheet, PDF (101/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
7 1 4 IER(A B) INTERRUPT ENABLE REGISTER
I O Address
Default Value
Attribute
Size
Base ^a1h (DLAB^e0)
00h
Read Write
8 bits
This register enables disables interrupts for five types of serial port conditions If a particular condition occurs
whose interrupt is disabled in this register the corresponding interrupt status bit in the IIR will not be set and
an interrupt request (IRQ3 or IRQ4) will not be generated
Figure 49 Interrupt Enable Register
290486 – 49
Bit
Description
7 4 RESERVED
3 MODEM INTERRUPT ENABLE (MIE) When MIE^e1 the Modem Status Interrupt is enabled When
MIE^e0 the Modem Status Interrupt is disabled
2 RECEIVER INTERRUPT ENABLE (RIE) When RIE^e1 the Receiver Line Status interrupt is
enabled When RIE^e0 the receiver line status interrupt is disabled
1 TRANSMITTER HOLDING REGISTER EMPTY INTERRUPT ENABLE (THEIE) When THREIE^e1
the Transmitter Holding Register Empty Interrupt is enabled When THREIE^e0 the Transmitter
Holding Register Empty Interrupt is disabled
0 RECEIVER DATA AVAILABLE INTERRUPT ENABLE AND TIMEOUT INTERRUPT ENABLE IN
FIFO MODE (RAVIE) When RAVIE^e1 the Received Data Available Interrupt is Enabled When
RAVIE^e0 the Received Data Available Interrupt is disabled In addition in the FIFO Mode this bit
enables the Timeout Interrupt when set to 1 and disables the Timeout Interrupt when set to 0
101