82091AA Datasheet, PDF (96/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
In the forward direction an interrupt occurs when
SERVICEINTR^e0 and there are either 8 or 1 byte
locations available in the FIFO (depending on
threshold setting) IRQ5 IRQ7 can be used in an in-
terrupt-driven system The host must respond to the
interrupt request by writing data to the FIFO
6 2 3 5 Data Compression
The 82091AA supports Run Length Encoded (RLE)
decompression in hardware and can transfer com-
pressed data to the peripheral To transfer com-
pressed data to the peripheral (forward direction)
the compression count is written to the ECPAFIFO
location and the data is written to the ECPDFIFO
location The most significant bit (bit 7) in the byte
written to the ECPAFIFO Register informs the pe-
ripheral whether the value is a channel address (bit
7^e1) or a run length count (bit 7^e0) The RLE
count in the ECPAFIFO (bits 6 0 ) informs the pe-
ripheral of how many times the data in the
ECPDFIFO is to be repeated An RLE count of 0
indicates that only one byte of the data is present
and a count of 127 indicates to the peripheral that
the next byte should be expanded 128 times An
RLE count of 1 should be avoided as it will cause
unnecessary expansions Note that the 82091AA
asserts AUTOFD to indicate that PD 7 0 contains
address RLE instead of data
82091AA decompresses (replicates) the next data
received by the RLE count received on bits 6 0
6 2 4 PARALLEL PORT EXTERNAL BUFFER
CONTROL
A multi-function signal (GCS PPDIR) is provided
for controlling optional external parallel port data
buffers The PPDIR function is only available when
the 82091AA configuration is in software mother-
board (SWMB) mode In this mode this signal oper-
ates as a parallel port direction control signal
(PPDIR) Note that if any other configuration is used
(SWAI HWB or HWE configuration modes) this
multi-function signal operates as a game port chip
select (GCS ) In SWMB PPDIR is low when
PD 7 0 are outputs and high when PD 7 0 are in-
puts Figure 44 shows an example of external buff-
ers being used when the parallel port is in ECP
mode
External buffering affects the ability of the port to
read software security devices Typically these soft-
ware secutiry devices are designed to hold the data
pins of the parallel port connector at either high or
low logic levels when the pins are not being driven
by the parallel port The bit pattern read from the
parallel port by the security software may not be cor-
rectly transferred through the external buffer
In the reverse direction the peripheral negates the
BUSY signal to indicate that PD 7 0 contains ad-
dress RLE During an address RLE cycle the
82091AA checks bit 7 to see if the next byte re-
ceived needs to be decompressed If bit 7 is 0 the
6 2 5 PARALLEL PORT SUMMARY
Table 18 summarizes the parallel port interrupt
DMA and parallel port signal drive type for the vari-
ous modes of operation
Table 18 Parallel Port Summary
Parallel Port
Mode
ECR 7 5
PD 7 0
Direction
Parallel Port
Control Signals
Controlled By PCON
IRQ Enable
DMA Enable
ISA-Compatible
000 Output
Open Drain
ACKINTEN
PS 2-Compatible
001 Bi-directional
Open Drain
ACKINTEN
EPP
N A Bi-directional
Push Pull
ACKINTEN
ISA-Compatible FIFO 010 Output
Push Pull
Always Enabled DMAEN
ECP
011 Bi-directional
Push Pull
Always Enabled DMAEN
ECP Test
110 Output
Push Pull
Always Enabled DMAEN
ECP Configuration
111 Bi-directional
Push Pull
ACKINTEN
DMAEN
NOTES
1 The selected IRQ pin (IRQ5 IRQ7) is enabled if ACKINTEN is enabled in the PCON Register Otherwise the IRQ pin is
tri-stated
2 PPDREQ is enabled whenever the DMAEN bit is enabled in the ECR independent of the parallel port mode
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