82091AA Datasheet, PDF (107/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
Bit
Description
7 DIVISOR LATCH ACCESS BIT (DLAB) DLAB controls access to the Baud Rate Generator Divisor
Latches (and to the Transmit Holding Register Receiver Buffer Register and Interrupt Enable
Register which are located at the same I O addresses) When DLAB^e1 access to the two Divisor
Latches is selected and access to the THR RBR and IER is disabled When DLAB^e0 access to
the two Divisor Latches is disabled and access to the THR RBR and IER is selected
During test mode operations DLAB must be set to 1 for the BOUT signal to appear on the SOUT
pin
6 BREAK CONTROL (BRCON) When BRCON^e1 a break condition is transmitted from the
82091AA serial port to the receiving device When BRCON^e1 the serial output (SOUT) is forced to
the ‘spacing‘ state (logical 0) BRCON only affects the SOUT signal and has no effect on the
transmitter logic Note that this feature permits the CPU to alert a terminal If the following sequence
is used no erroneous characters will be transmitted because of the break
1 Wait for the transmitter to be idle (TEMT^e1)
2 Set break (BRCON^e1) for the appropriate amount of time If the transmitter will be used to time
the break duration then check that TEMT^e1 before clearing the BRCON
3 Clear break (BRCON^e0) when normal transmission has to be restored
During the break the transmitter can be used as a character timer to accurately establish the break
duration by sending characters and monitoring THRE and TEMT
5 STICKY PARITY (STICPAR) STICPAR is the Stick Parity bit When parity is enabled (PAREN^e1)
this bit is used in conjunction with EVENPAR to select ‘‘Mark’’ or ‘‘Space’’ Parity When bits PAREN
EVENPAR and STICPAR are 1 the parity bit is transmitted and checked as a 0 (Space Parity) If bits
PAREN and STICPAR are 1 and EVENPAR is 0 the parity bit is transmitted and checked as a 1
(Mark Parity) When STICPAR^e0 stick parity is disabled
4 EVEN PARITY SELECT (EVENPAR) EVENPAR selects between even and odd parity When parity
is enabled (PAREN^e1) and EVENPAR^e0 an odd number of 1s is transmitted or checked in the
data word bits and parity bit When parity is enabled and EVENPAR^e1 an even number of 1s is
transmitted or checked
3 PARITY ENABLE (PAREN) This bit enables disables parity generation and checking When
PAREN^e1 a parity bit is generated (transmit data) or checked (receive data) between the last data
bit and stop bit of the serial data (The Parity bit is used to produce an even or odd number of 1s
when the data bits and the Parity bit are summed ) When PAREN^e0 parity generation and
checking is disabled
2 STOP BITS (STOPB) This bit specifies the number of stop bits transmitted with each serial
character When STOPB^e0 one stop bit is generated in the transmitted data When STOPB^e1
and a 5-bit data length is selected one and a half stop bits are generated When STOPB^e1 and
either a 6- 7- or 8-bit data length is selected two stop bits are generated The receiver checks the
first Stop bit only regardless of the number of Stop bits selected
1 0 SERIAL DATA BITS (SERIALDB) This field specifies the number of data bits in each transmitted or
received serial character as follows
Bits 1 0
00
01
10
11
Data Length
5 Bits - Default
6 Bits
7 Bits
8 Bits
107