82091AA Datasheet, PDF (26/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
2 7 Hard Reset Signal Conditions
Table 1 shows the state of all 82091AA output and bi-directional signals during hard reset (RSTDRV asserted)
The strapping options described in Section 4 0 AIP Configuration are sampled when the 82091AA is hard
reset
Table 2 Output and I O Signal States During a Hard Reset
Signal Name
ACK
AEN
AUTOFD
BUSY
CTS A B
DCD A B
DEN
DIR
DRVDEN 1 0 0
DSKCHG
DTR A B
FAULT
FDDACK
FDDREQ
FDME0 MEEN
FDME1 DSEN
FDS0 MDS0
FDS1 MDS1
State
Tri-state
High
High⁽¹⁾
High
Low
High⁽¹⁾
Tri-state
High
High
High
High
Signal Name
HDSEL
HEN
IDECS 1 0
INDX
INIT
IO16
IOCHRDY
IORC
IOWC
IRQ 7 3
NOWS
PD 7 0
PERROR
PPDACK
PPDREQ
PPDIR GCS
RDDATA
RI A B
State
High
High⁽¹⁾
High⁽¹⁾
Low
Tri-state⁽²⁾
Tri-state
Tri-state
Low
Tri-state
High⁽¹⁾
Signal Name
RSTDRV
RTS A B
SA 10 0
SD 7 0
SELECT
SELECTIN
SIN A B
SOUT A B
STEP
STROBE
TC
TRK0
WE
WP
WRDATA
X1 OSC
X2
State
High⁽¹⁾
Tri-state
Tri-state
High⁽¹⁾
High
Tri-state
High
High
NOTES
1 During and immediately after a hard reset this signal is an input for hardware configuration After the hardware configura-
tion time these signals go to the state specified in the table
2 If IORC or IOWC is asserted IOCHRDY will be asserted by the IOCHRDY
3 Dashes represent input signals
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