82091AA Datasheet, PDF (143/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

Symbol
MIN DLY
MT
N
NCN
ND
NRP
OW
82091AA
Description
MINIMUM POWERUP TIME CONTROL This bit is active only if AUTO PD bit is enabled
When MIN DLY^e0 a 10 ms minimum powerup time is assigned and when MIN DLY^e1 a
0 5 sec minimum powerup time is assigned
MULTI-TRACK SELECTOR When MT^e1 the multi-track operating mode is selected In
this mode the FDC treats a complete cylinder under head 0 and 1 as a single track The
FDC operates as if this expanded track started at the first sector under head 0 and ended at
the last sector under head 1 With this flag set a multitrack read or write operation will
automatically continue to the first sector under head 1 when the FDC finishes operating on
the last sector under head 0
SECTOR SIZE CODE This specifies the number of bytes in a sector When N^e00h the
sector size is 128 bytes The number of bytes transferred is determined by the DTL parame-
ter Otherwise the sector size is (2 raised to the ‘‘N’th’’ power) times 128 All values up to
07h are allowable A value of 07h equals a sector size of 16 Kbytes It is the users responsi-
bility to not select combinations that are not possible with the drive
N Sector Size
00 128 bytes
01 256 bytes
02 512 bytes
03
1024
07 16 Kbytes
NEW CYLINDER NUMBER The desired cylinder number
NON-DMA MODE FLAG When ND^e1 the FDC operates in the non-DMA mode In this
mode the host is interrupted for each data transfer When ND^e0 the FDC operates in DMA
mode and interfaces to a DMA controller by means of the DRQ and DACK signals
NO RESULTS PHASE When NRP^e1 the result phase is skipped When NRP^e0 the
result phase is generated
OVERWRITTEN The bits denoted D0 and D1 of the PERPENDICULAR MODE Command
can only be overwritten when OW^e1
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