82091AA Datasheet, PDF (114/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
7 2 FIFO Operations
This section describes the FIFO operations for inter-
rupt and polled modes
7 2 1 FIFO INTERRUPT MODE OPERATION
When the Receive FIFO and receiver interrupts are
enabled (FCR0^e1 and IER0^e1) receiver interrupts
occur as follows
1 The receive data available interrupt is invoked
when the FIFO has reached its programmed trig-
ger level The interrupt is cleared when the FIFO
drops below the programmed trigger level
2 The IIR receive data available indication also oc-
curs when the FIFO trigger level is reached and
like the interrupt the bits are cleared when the
FIFO drops below the trigger level
3 The receiver line status interrupt (IIR-06h) as be-
fore has higher priority than the received data
available (IIR^e04h) interrupt
4 The data ready bit (LSR0) is set as soon as a
character is transferred from the shift register to
the receive FIFO This bit is set to 0 when the
FIFO is empty
When receiver FIFO and receiver interrupts are en-
abled receiver FIFO timeout interrupts occur as fol-
lows
1 A FIFO timeout interrupt occurs if the following
conditions exist
a At least one character is in the FIFO
b The most recent serial character received was
longer than 4 continous character times ago (if
2 stop bits are programmed the second one is
included in this time delay)
c The most recent CPU read of the FIFO was
longer than 4 continous character times ago
The maximum time between a received charac-
ter and a timeout interrupt is 160 ms at 300
baud with a 12-bit receive character (i e 1
start 8 data 1 parity and 2 stop bits)
2 Character times are calculated by using the RCLK
input for a clock signal (this makes the delay pro-
portional to the baud rate)
3 When a timeout interrupt occurs it is cleared and
the timer reset when the CPU reads one charac-
ter from the receiver FIFO
4 When a timeout interrupt does not occur the
timeout timer is reset after a new character is re-
ceived or after the CPU reads the receiver FIFO
When the transmit FIFO and transmitter interrupts
are enabled (FCR0^e1 IER1^e1) transmit interrupts
occur as follows
1 The transmitter holding register interrupt occurs
when the transmit FIFO is empty The interrupt is
cleared as soon as the transmitter holding regis-
ter is written (1 to 16 characters may be written to
the transmit FIFO while servicing the interrupt) or
the IIR is read
Character timeout and receiver FIFO trigger level in-
terrupts have the same priority as the current re-
ceived data available interrupt Transmit FIFO empty
has the same priority as the current transmitter hold-
ing register empty interrupt
7 2 2 FIFO POLLED MODE OPERATION
With FIFO^e1 setting IER 3 0 to all 0s puts the se-
rial port in the FIFO polled mode of operation Since
the receiver and transmitter are controlled separate-
ly either one or both can be in the polled mode of
operation
In this mode software checks receiver and transmit-
ter status via the LSR As stated in the register de-
scription
 LSR0 is set as long as there is one byte in the
receiver FIFO
 LSR1 and LSR4 specify which error(s) has oc-
curred Character error status is handled the
same way as interrupt mode The IIR is not af-
fected since IER2^e0
 LSR5 indicates when the transmitter FIFO is
empty
 LSR6 indicates that both the transmitter FIFO
and shift register are empty
 LSR7 indicates whether there are any errors in
the receiver FIFO
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