82091AA Datasheet, PDF (37/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
4 1 7 FCFG2 FDC POWER MANAGEMENT AND STATUS REGISTER
Index Address
Default Value
Attribute
Size
11h
RRRR 0000
Read Write
8 bits
This register enables disables FDC auto powerdown and can place the FDC into direct powerdown The
register also provides FDC idle status and FDC reset control
Figure 10 FDC Power Management and Status Register
290486 – 10
Bit
Description
7 4 RESERVED
3 FLOPPY DISK AUTO POWERDOWN ENABLE (FAPDN) This bit is used to enable disable auto
powerdown for the FDC When FAPDN^e1 the FDC will enter auto powerdown when the required
conditions are met When FAPDN^e0 FDC auto powerdown is disabled
2 FLOPPY DISK CONTROLLER RESET (FRESET) FRESET is a reset for the FDC When
FRESET^e1 the FDC is reset (i e all programming and current state information is lost)
FRESET^e1 has the same affect on the FDC as a hard reset (asserting the RSTDRV signal) When
resetting the FDC via this configuration bit the software must toggle this bit and ensure the reset
active time (FRESET^e1) of 1 13 ms minimum is met
1 FLOPPY DISK CONTROLLER IDLE STATUS (FIDLE) When the FDC is in the idle state this bit is
set to 1 by the 82091AA hardware In the idle state the FDC’s Main Status Register (MSR)^e80h
IRQ6^einactive and the head unload timer has expired When the FDC exits its idle state this bit is
set to 0 This bit is read only
0 FLOPPY DISK CONTROLLER POWERDOWN (FDPDN) When FDPDN is set to 1 the FDC is
placed in direct powerdown Once in powerdown the following procedure should be used to bring
the FDC out of powerdown
 Write this bit low
 Apply a hardware reset (via bit 2 of this register) or a software reset (via either bit 2 of the FDC’s
DOR or bit 7 of the FDC’s DSR)
NOTE
A hard reset via the RSTDRV pin also removes the FDC powerdown
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