82091AA Datasheet, PDF (73/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
Bit
Description
7 6 RESERVED
5 DIRECTION (DIR ) This bit is used to control the direction of data transfer on the parallel port data
bus (PD 7 0 ) When DIR ^e0 (forward direction) PD 7 0 are outputs When DIR ^e1 (reverse
direction) PD 7 0 are inputs
4 ACK INTERRUPT ENABLE (ACKINTEN) ACKINTEN enables CPU interrupts (via IRQ5 or IRQ7)
to be generated when the ACK signal on the parallel port interface is asserted When
ACKINTEN^e1 a CPU interrupt is generated when ACK is asserted When ACKINTEN^e0 the
ACK interrupt is disabled
3 SELECTIN CONTROL (SELINC) Write to 0 when programming this register This bit must be 0 for
the parallel port handshake to operate properly
2 INIT CONTROL (INITC) This bit controls the INIT signal When INITC^e1 the INIT signal is
negated When INITC^e0 the INIT signal is asserted
1 AUTOFD CONTROL (AUTOFDC) Write to 0 when programming this register
0 STROBE CONTROL (STROBEC) Write to 0 when programming this register This bit must be 0
for the parallel port handshake to operate properly
6 1 2 4 ADDSTR EPP Auto Address Strobe Register (EPP Mode)
I O Address
Default Value
Attribute
Size
Base ^a03h
00h
Read Write
8 bits
The ADDSTR Register provides a peripheral address to the peripheral (via PD 7 0 ) during a host address
write operation and to the host (via PD 7 0 ) during a host address read operation An automatic address
strobe is generated on the parallel port interface when data is read from or written to this register
Bit
Description
7 0 EPP ADDRESS Bits 7 0 correspond to SD 7 0 and PD 7 0
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