82091AA Datasheet, PDF (5/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

CONTENTS
6 2 3 1 FIFO Operations
6 2 3 2 DMA Transfers
6 2 3 3 Reset FIFO and DMA Terminal Count Interrupt
6 2 3 4 Programmed I O Transfers
6 2 3 5 Data Compression
6 2 4 PARALLEL PORT EXTERNAL BUFFER CONTROL
6 2 5 PARALLEL PORT SUMMARY
7 0 SERIAL PORT
7 1 Register Description
7 1 1 THR(A B) TRANSMITTER HOLDING REGISTER
7 1 2 RBR(A B) RECEIVER BUFFER REGISTER
7 1 3 DLL(A B) DLM(A B) DIVISOR LATCHES (LSB AND MSB) REGISTERS
7 1 4 IER(A B) INTERRUPT ENABLE REGISTER
7 1 5 IIR(A B) INTERRUPT IDENTIFICATION REGISTER
7 1 6 FCR(A B) FIFO CONTROL REGISTER
7 1 7 LCR(A B) LINE CONTROL REGISTER
7 1 8 MCR(A B) MODEM CONTROL REGISTER
7 1 9 LSR(A B) LINE STATUS REGISTER
7 1 10 MSR(A B) MODEM STATUS REGISTER
7 1 11 SCR(A B) SCRATCHPAD REGISTER
7 2 FIFO Operations
7 2 1 FIFO INTERRUPT MODE OPERATION
7 2 2 FIFO POLLED MODE OPERATION
8 0 FLOPPY DISK CONTROLLER
8 1 Floppy Disk Controller Registers
8 1 1 SRB STATUS REGISTER B (EREG EN^e1)
8 1 2 DOR DIGITAL OUTPUT REGISTER
8 1 3 TDR ENHANCED TAPE DRIVE REGISTER
8 1 4 MSR MAIN STATUS REGISTER
8 1 5 DSR DATA RATE SELECT REGISTER
8 1 6 FDCFIFO FDC FIFO (DATA)
8 1 7 DIR DIGITAL INPUT REGISTER
8 1 8 CCR CONFIGURATION CONTROL REGISTER
8 2 Reset
8 2 1 HARD RESET AND CONFIGURATION REGISTER RESET
8 2 2 DOR RESET vs DSR RESET
8 3 DMA Transfers
8 4 Controller Phases
8 4 1 COMMAND PHASE
8 4 2 EXECUTION PHASE
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