82091AA Datasheet, PDF (102/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
7 1 5 IIR(A B) INTERRUPT IDENTIFICATION REGISTER
I O Address
Default Value
Attribute
Size
Base ^a2h
01h
Read Only
8 bits
This register provides interrupt status and indicates whether the serial port receive transmit FIFOs are en-
abled (FIFO mode) or disabled (non-FIFO mode) In order to provide minimum software overhead during data
character transfers the serial port prioritizes interrupts into four levels and records these in the Interrupt
Identification Register The four levels of interrupt conditions in order of priority are Receiver Line Status
Received Data Ready Transmitter Holding Register Empty and Modem Status When the CPU accesses the
IIR the serial port freezes all interrupts and indicates the highest priority pending interrupt to the CPU While
this CPU access is occurring the serial port records new interrupts but does not change its current indication
until the current access is complete
Figure 50 Interrupt Identification Register
290486 – 50
102