82091AA Datasheet, PDF (86/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
Bit
Description
7 5 ECP MODE SELECT This field selects one of the following ECP Modes
Mode
000
Operation
ISA-Compatible Mode In this mode the parallel port operates in ISA-Compatible mode
The FIFO is reset and common collector drivers are used on the control lines (STROBE
AUTOFD INIT and SELECTIN ) Setting the direction bit to 1 in the PCON Register
does not affect the parallel port interface For register descriptions in this mode See
Section 6 1 1 ISA-Compatible and PS 2-Compatible Modes
001
PS 2-Compatible Mode In this mode the parallel port operates in PS 2-Compatible
mode The FIFO is reset and common collector drivers are used on the control lines
(STROBE AUTOFD INIT and SELECTIN ) Unlike mode 000 above setting the
direction bit to 1 in the PCON Register tri-states the data lines and reading the data
register returns the value on the PD 7 0 For register descriptions in this mode see
Section 6 1 1 ISA-Compatible and PS 2-Compatible Modes
010
ISA-Compatible FIFO Mode This mode is the same as mode 000 above except that
data is written or DMAed to the FIFO FIFO data is automatically transmitted using the ISA-
style protocol For this mode the direction control bit in the PCON register must be 0
011
ECP Mode In the forward direction bytes written to the ECP DFIFO location and bytes
written to the ECP AFIFO location are placed in the ECP FIFO and transmitted
automatically to the peripheral using ECP protocol In reverse direction bytes are
transferred from PD 7 0 to the ECP FIFO
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Test Mode In this mode the FIFO may be written and read but the data will not be
transmitted on PD 7 0
1 1 1 Configuration Mode In this mode the ECP Configuration A and B Registers are
accessible
ECP Mode Switching Guidelines
Software will execute P1284 negotiations and all operation prior to a data transfer phase under
programmed I O (using mode 000 or 001) Hardware provides an automatic control line handshake
moving data between the FIFO and the ECP port only in the data transfer phase (using modes 011
or 010)
Setting the mode to 011 or 010 causes the hardware to initiate the data transfer
If the parallel port is in mode 000 or 001 the port can be switched to any other mode If the parallel
port is not in mode 000 or 001 the port can only be switched into mode 000 or 001 The direction
and the FIFO threshold can only be changed in modes 000 or 001 Note that the FIFO FIFO Error
and TC conditions are also reset when the mode is switched to 000 or 001
Once in an extended forward mode the software should wait for the FIFO to be empty before
switching back to mode 000 or 001 In this case all control signals are negated before the mode
switch In an ECP reverse mode the software waits for all the data to be read from the FIFO before
changing to mode 000 or 001
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