82091AA Datasheet, PDF (163/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
10 0 POWER MANAGEMENT
The 82091AA provides power management capabili-
ties for its primary functional modules (parallel port
floppy disk controller serial port A and serial port
B) For each module the 82091AA implements two
types of power management direct powerdown
and auto powerdown Direct powerdown enabled
via control bits in the 82091AA configuration regis-
ters immediately places the module in a powerdown
mode by turning off the clock to the associated mod-
ule Direct powerdown removes the clock regardless
of the activity or status of the module By contrast
when auto powerdown is enabled (via control bits in
the 82091AA configuration registers) the associated
module only enters a powerdown mode if it is in an
idle state
NOTE
The entire 82091AA can be placed in direct
powerdown by writing to the CLKOFF bit in
the AIPCFG1 Register
10 1 Power Management Registers
The floppy disk controller parallel port serial port A
and serial port B each have two 82091AA configura-
tion registers For each module three configuration
register bits control power management xDPDN
xIDLE and xAPDN
 xAPDN auto-powerdown shuts off the oscillator
to the module when the module is idle
 xIDLE idle status a read only pin that indicates
idle status
 xDPDN direct powerdown shuts off module os-
cillator when active regardless of module status
The 82091AA exits any powerdown mode after a
hardware reset (RSTDRV asserted) or reset via the
xRESET bit in the 82091AA configuration registers
Direct powerdown can also be exited by writing the
corresponding xPDN bit in the configuration register
to 0 Auto powerdown is exited by events at the
module (e g CPU read write or module interface
activity)
NOTE
The configuration registers also contain the
xEN bit This bit is used to completely dis-
able an unused module Enabling a disabled
module takes much longer than restoring a
module from powerdown Therefore this bit
is not recommend for temporarily disabling a
module as a powerdown scheme
10 2 Clock Power Management
The internal clock circuitry of the 82091AA can be
turned on or off as part of a power management
scheme The clock circuitry is controlled via the
CLKOFF bit in the AIPCFG1 Register If an external
clock source exists the user may want to turn off the
internal oscillator to save power and provide mini-
mum recovery time
Auto powerdown and direct powerdown (in each
module) have no effect on the state of internal oscil-
lator
10 3 FDC Power Management
This section describes the FDC direct and auto pow-
erdown modes and recovery from the powerdown
modes
Auto Powerdown
Automatic powerdown (APDN) has an advantage
over direct powerdown (PDN) since the register con-
tents are not lost under APDN Automatic power-
down is invoked by either the Auto Powerdown com-
mand or by enabling the FAPDN bit in the FDC con-
figuration register There are four conditions required
before the FDC will enter powerdown
1 The motor enable pins ME 3 0 must be inactive
2 The FDC must be in an idle state FDC idle is
indicated by MSR^e80h and the IRQ6 signal is
negated (IRQ6 may be asserted even if
MSR^e80h due to polling interrupt)
3 The head unload timer (HUT explained in the
SPECIFY Command) must have expired
4 The auto powerdown timer must have timed out
An internal timer is initiated when the POWER-
DOWN MODE Command is executed The amount
of time can be set by the user via the MIN DLY bits
in the POWERDOWN MODE Command The mod-
ule is then powered down provided all the remaining
conditions are met A software reset reinitializes the
timer When using the FDC FAPDN bit to enable the
automatic powerdown feature the MIN DLY bit is set
to the default condition
Recovery from Auto Powerdown
When the FDC is in auto powerdown the module is
awakened by a reset or access to the DOR MSR or
FIFO registers The module remains in auto power-
down mode after a software reset (i e it will power-
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