82091AA Datasheet, PDF (129/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
8 4 2 EXECUTION PHASE
The following paragraphs detail the operation of the
FIFO flow control In these descriptions threshold is
defined as the number of bytes available to the FDC
when service is requested from the host and ranges
from 1 to 16 The FIFOTHR parameter which the
user programs is one less and ranges from 0 to 15
A low threshold value (e g 2) results in longer peri-
ods of time between service requests but requires
faster servicing of the request for both read and
write cases The host reads (writes) from (to) the
FIFO until empty (full) then the transfer request
goes inactive The host must be very responsive to
the service request This is the desired case for use
with a ‘‘fast’’ system
A high value of threshold (e g 12) is used with a
‘‘sluggish’’ system by affording a long latency period
after a service request but results in more frequent
service requests
8 4 2 1 Non-DMA Mode Transfers from the FIFO
to the Host
The IRQ6 pin and RQM bits in the Main Status Reg-
ister are activated when the FIFO contains 16 (or set
threshold) bytes or the last bytes of a full sector
transfer have been placed in the FIFO The IRQ6 pin
can be used for interrupt driven systems and RQM
can be used for polled sytems The host must re-
spond to the request by reading data from the FIFO
This process is repeated until the last byte is trans-
ferred out of the FIFO then FDC negates the IRQ6
pin and RQM bit
8 4 2 2 Non-DMA Mode Transfers from the Host
to the FIFO
The IRQ6 pin and RQM bit in the Main Status Regis-
ter are activated upon entering the execution phase
of data transfer commands The host must respond
to the request by writing data into the FIFO The
IRQ6 pin and RQM bit remain true until the FIFO
becomes full They are set true again when the FIFO
has (threshold) bytes remaining in the FIFO The
IRQ6 pin is also negated if TC and DACK both go
inactive The FDC enters the result phase after the
last byte is taken by the FDC from the FIFO (i e
FIFO empty condition)
8 4 2 3 DMA Mode Transfers from the FIFO to
the Host
The FDC asserts the FDDREQ signal when the FIFO
contains 16 (or set threshold) bytes or the last byte
of a full sector transfer has been placed in the FIFO
The DMA controller must respond to the request by
reading data from the FIFO The FDC negates
FDDREQ when the FIFO is empty FDDREQ is neg-
ated after FDDACK is asserted for the last byte of
a data transfer (or on the active edge of RD on
the last byte if no edge is present on FDDACK )
NOTE
FDDACK and TC must overlap for at least
50 ns for proper functionality A data under-
run may occur if FDDREQ is not removed in
time to prevent an unwanted cycle
8 4 2 4 DMA Mode Transfers from the Host to
the FIFO
The FDC asserts FDDREQ when entering the exe-
cution phase of data transfer commands The DMA
controller must respond by asserting FDDACK and
WR signals and placing data in the FIFO
FDDREQ remains asserted until the FIFO becomes
full FDDREQ is again asserted when the FIFO has
(threshold) bytes remaining in the FIFO The FDC
also negates the FDDREQ when the FIFO becomes
empty (qualified by DACK and TC overlapping by
50 ns) indicating that no more data is required
FDDREQ is negated after FDDACK is asserted for
the last byte of a data transfer (or on the active edge
of WR of the last byte if no edge is present on
DACK ) A data overrun may occur if FDDREQ is
not removed in time to prevent an unwanted cycle
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