82091AA Datasheet, PDF (61/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
5 0 HOST INTERFACE
The 82091AA host interface is an 8-bit direct-drive
(24 mA) ISA Bus X-Bus interface that permits the
CPU to access its registers through read write oper-
ations in I O space These registers may be ac-
cessed by programmed I O and or DMA bus cycles
With the exception of the IDE Interface all functions
on the 82091AA require only 8-bit data accesses
The 16-bit access required for the IDE Interface is
supported through the appropriate chip selects and
data buffer enables from the 82091AA The
82091AA does not participate in 16-bit IDE DMA
transfers
Although the 82091AA has an ISA X-Bus host inter-
face there are a few features that differentiate it
from conventional ISA X-Bus peripherals These
features are as follows
 Internal Configurable Chip Select Decode
Logic SA 9 0 allow full decoding of the ISA I O
address space such that the functional modules
contained in the 82091AA can be relocated to
the desired I O address This feature can be
used to resolve potential system configuration
conflicts
 IOCHRDY for ISA Cycle Extension During cer-
tain I O cycles to the parallel port controller in the
82091AA it is necessary to extend the current
bus cycle to match the access time of the device
connected to the Parallel Port The
IOCHRDY signal is used by the 82091AA to ex-
tend ISA Bus cycles as needed according to the
ISA protocol IOCHRDY overrides all other
strobes that attempt to shorten the bus cycle
 NOWS for 3 BCLK I O Cycles All pro-
grammed I O accesses to 82091AA registers
can be completed in a total of 3 BCLK cycles
This is possible because the 82091AA register
access times have been minimized to allow data
transfers to occur with shortened read write con-
trol strobes As a result the 82091AA is well suit-
ed for use in embedded control designs that use
an asynchronous microprocessor interface with-
out any particular reference to ISA cycle timings
 DMA Transfers The 82091AA supports DMA
compatible type A type B and type F DMA cy-
cles Some newer system DMA controllers are
capable of generating fast DMA cycles (type F)
on all DMA channels If such a controller is used
in conjunction with the 82091AA it will be possi-
ble to accomplish a DMA transfer in 2 BCLKs
The 82091AA ISA data lines (SD 7 0 ) can be con-
nected directly to the ISA Bus If external buffers are
used to isolate the SD 7 0 signals from the 240 pF
loading of the ISA Bus the DEN signal can be
used to control the external buffers as shown in Fig-
ure 25
290486 – 25
Figure 25 ISA Interface (with Optional Data Buffer)
61