82091AA Datasheet, PDF (121/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
8 1 4 MSR MAIN STATUS REGISTER
I O Address
Default Value
Attribute
Size
Base ^a4h
00h
Read Only
8 bits
This read only register provides FDC status information This information is used by software to control the
flow of data to and from the FIFO (accessed via the FDCFIFO Register) The MSR indicates when the FDC is
ready to send or receive data through the FIFO During non-DMA transfers this register should be read before
each byte is transferred to or from the FIFO
After a hard or soft reset or recovery from a powerdown state the MSR is available to be read by the host The
register value is 00h until the oscillator circuit has stabilized and the internal registers have been initialized
When the FDC is ready to receive a new command MSR 7 0 ^e80h The worst case time allowed for the MSR
to report 80h (i e RQM is set to 1) is 2 5 ms after a hard or soft reset
Main Status Register is used for controlling command input and result output for all commands Some example
values of the MSR are
 MSR^e80H The controller is ready to receive a command
 MSR^e90H executing a command or waiting for the host to read status bytes (assume DMA mode)
 MSR^eD0H waiting for the host to write status bytes
Figure 59 Main Status Register
290486-59
121