82091AA Datasheet, PDF (119/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
Bit
Description
7 6 RESERVED For a two-drive system these bits are not used and have no affect on FDC operation
For a four drive system see Appendix A FDC Four Drive Support
5 MOTOR ENABLE 1 (ME1) This bit controls a motor drive enable signal ME1 directly controls either
the FDME1 signal or FDME0 signal depending on the state of the BOOTSEL bit in the TDR
When ME1^e1 the selected motor enable signal (FDME1 or FDME0 ) is asserted and when
ME1^e0 the selected motor enable signal is negated
4 MOTOR ENABLE 0 (ME0) This bit controls a motor drive enable signal ME1 directly controls either
the FDME0 signal or FDME1 signal depending on the state of the BOOTSEL bit in the TDR
When ME0^e1 the selected motor enable signal (FDME0 or FDME1 ) is asserted and when
ME0^e0 the selected motor enable signal is negated
3 DMA GATE (DMAGATE) This bit enables disables DMA for the FDC When DMAGATE^e1 DMA
for the FDC is enabled In this mode FDDREQ TC IRQ6 and FDDACK are enabled When
DMAGATE^e0 DMA for the FDC is disabled In this mode the IRQ6 and DRQ outputs are tri-stated
and the DACK and TC inputs are disabled to the FDC Note that the TC input is only disabled to
the FDC module Other functional units in the 82091AA (e g parallel port or IDE interface) can still
use the TC input signal for DMA activities
2 FDC RESET (DORRST) DORRST is a software reset for the FDC module When DORRST is set to
0 the basic core of the FDC and the FIFO circuits are cleared conditioned by the LOCK bit in the
CONFIGURE Command This bit is set to 0 by software or a hard reset (RSTDRV asserted) The
FDC remains in a reset state until software sets this bit to 1 This bit does not affect the DSR CCR
and other bits of the DOR DORRST must be held active for at least 0 5 ms at 250 Kbps This is less
than a typical ISA I O cycle time Thus in most systems consecutive writes to this register to toggle
this bit allows sufficient time to reset the FDC
1 RESERVED For a two-drive system this bit is not used and must be programmed to 0 For a four
drive system see Appendix A FDC Four Drive Support
0 DRIVE SELECT (DS) This selects the floppy drive by controlling the FDS0 and FDS1 output
signals DS directly controls FDS1 and FDS0 as follows
Bit 0
0
1
Output Pin Status
FDS0 asserted (FDS1 asserted if BOOTSEL^e1)
FDS1 asserted (FDS1 asserted if BOOTSEL^e1)
8 1 3 TDR ENHANCED TAPE DRIVE REGISTER
I O Address
Default Value
Attribute
Size
Base ^a3h
00h
Read Write
8 bits
This register allows the user to assign tape support to a particular drive during initialization Any future refer-
ences to that drive number automatically invokes tape support A hardware reset sets all bits in this register to
0 making drive 0 not available for tape support A software reset via bit 2 of the DOR does not affect this
register Drive 0 is reserved for the floppy boot drive Bits 7 2 are only available when EREG EN^e1 other-
wise the bits are tri-stated EREG EN is a bit in the POWERDOWN Command
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