82091AA Datasheet, PDF (19/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
2 4 IDE Interface (Continued)
Signal
Name
Type
Description
DEN
I O DATA ENABLE DEN is an output during normal system operations and is a data
enable for an external data buffer for all 82091AA and IDE accesses The SD 7 0
signals can be connected directly to the ISA In this case the DEN signal is not used
However an external buffer can be used to isolate the SD 7 0 signals from the 240 pF
loading of the ISA Bus With an external buffer implementation DEN controls the
external buffers for transfers to from the ISA Bus
Hardware Configuration
This signal is only an input during hardware configuration time (RSTDRV asserted)
(See Section 4 0 AIP Configuration )
HEN I O IDE UPPER DATA TRANSCEIVER ENABLE HEN is an output during normal system
operations and is a high byte data transceiver enable signal for the IDE hard disk drive
interface HEN is asserted for I O accesses to the IDE data register when the drive
asserts IO16
Hardware Configuration
This signal is only an input during hardware configuration time (RSTDRV asserted)
(See Section 4 0 AIP Configuration )
2 5 Parallel Port External Buffer Control Game Port
Signal
Name
Type
Description
PPDIR GCS
I O PARALLEL PORT DIRECTION (PPDIR) or GAME PORT CHIP SELECT
(GCS ) This signal is an output during normal operations and provides the
PPDIR and GCS functions as follows
PPDIR
This signal pin functions as a parallel port direction control output when the
82091AA is configured for software motherboard mode (SWMB) For
configuration details see Section 4 0 AIP Configuration If external buffers are
used on PD 7 0 PPDIR can be used to control the buffer direction The
82091AA drives this signal low when PD 7 0 are outputs and the 82091AA
drives this signal high when PD 7 0 are inputs Note that if a configuration
mode other than SWMB is selected this signal pin is a game port chip select
and does not track the PD 7 0 signal direction
GCS
This signal pin functions as a game port chip select output when 82091AA
configuration is set for Software Add-In (SWAI) Hardware Basic (HWB) or
Hardware Extended (HWE) modes When the host accesses I O address 201h
GCS is asserted
Hardware Configuration
This signal is only an input during hardware configuration time (RSTDRV
asserted) (See Section 4 0 AIP Configuration )
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