82091AA Datasheet, PDF (117/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
8 1 1 SRB STATUS REGISTER B (EREG EN^e1)
I O Address
Default Value
Attribute
Size
Base ^a1h
RRRR RRXX
Read Write
8 bits
SRB provides status and control information when auto powerdown is enabled In the AT EISA mode the SRB
is made available whenever the EREG EN bit in the POWERDOWN MODE Command is set to 1 When EREG
EN bit is set to 0 this register is not accessible In this case writes have no affect and reads return indetermi-
nate values
NOTE
XeValue is determined by the state of the corresponding signal pin
Figure 56 Status Register B
290486 – 56
Bit
Description
7 2 RESERVED
1 POWERDOWN STATUS (PD) This bit reflects the powerdown state of the FDC module The
82091AA sets PD to 1 when the FDC is in the powerdown state When PD^e0 the FDC is not in the
powerdown state
0 IDLE STATUS (IDLE) This bit reflects the idle state of the FDC module The 82091AA sets IDLE to
1 when the FDC is in the idle state When IDLE^e0 the FDC is not in the idle state
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