82091AA Datasheet, PDF (69/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
6 1 2 EPP MODE
This section contains the registers used in EPP mode The I O address assigment for this register set is shown
in Table 16 and the register descriptions are presented in the order that they appear in the table
Table 16 Parallel Port Registers (EPP Mode)
Parallel Port Register
Address Access
(AEN^e0) Base ^a
0h
1h
2h
3h
4h – 7h
Abbreviation
PDATA
PSTAT
PCON
ADDSTR
DATASTR
Register Name
Data Register
Status Register
Control Register
Address Strobe Register
Data Strobe Registers
Access
RW
RO
RW
RW
RW
NOTE
Parallel port base addresses are 278h (LPT2) and 378h (LPT1) Base address 3BCh is not available in EPP or ECP modes
6 1 2 1 PDATA Parallel Port Data Register (EPP Mode)
I O Address
Default Value
Attribute
Size
Base ^a00h
00h
Read Write
8 bits
The PDATA Register is a bi-directional data port that transfers 8-bit data between the peripheral device and
host The direction of transfer is determined by the DIR bit in the PCON Register If DIR ^e0 (forward
direction) and the host writes to this register the data is stored in the PDATA Register and driven onto
PD 7 0 If DIR ^e1 (reverse direction) a host read of this register returns the data on PD 7 0 However read
data is not stored in the PDATA Register
Bit
Description
7 0 PARALLEL PORT DATA Bits 7 0 correspond to parallel port data lines PD 7 0 and ISA Bus data
lines
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