82091AA Datasheet, PDF (74/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
6 1 2 5 DATASTR Auto Data Strobe Register (EPP Mode)
I O Address
Default Value
Attribute
Size
Base ^a04h 05h 06h 07h
00h
Read Write
8 bits
The DATASTR Register provides data from the host to the peripheral device (via PD 7 0 ) during host write
operations and from the peripheral device to the host (via PD 7 0 ) during a host read operation An automatic
data strobe is generated on the parallel port interface when data is read from or written to this register To
maintain compatibility with Intel’s 82360SL I O device that has a 32-bit Host Bus interface four consecutive
byte address locations are provided for transferring data
Bit
Description
7 0 EPP DATA Bits 7 0 correspond to SD 7 0 and PD 7 0
6 1 3 ECP MODE
This section contains the registers used in ECP mode The I O address assignment for this register set is
shown in Table 17 and the register descriptions are presented in the order that they appear in the table The
Extended Control Register (ECR) permits various modes of operation Note that ECR 7 5 ^e000 selects ISA-
Compatible mode and ECR 7 5 ^e001 selects PS 2-Compatibile mode These modes are discussed in Sec-
tion 6 1 1 ISA-Compatible and PS 2 Compatible modes The other modes selected by ECR 7 5 are dis-
cussed in this section
Table 17 Parallel Port Registers (ECP Mode)
Parallel Port
Register Address
Access (AEN^e0)
Base ^a
0h
1h
2h
400h
400h
400h
400h
401h
402h
Abbreviation
ECPAFIFO
PSTAT
PCON
SDFIFO
ECPDFIFO
TFIFO
ECPCFGA
ECPCFGB
ECR
Register Name
ECP Address RLE FIFO
Status Register
Control Register
Standard Parallel Port Data FIFO
ECP Data FIFO
Test FIFO
ECP Configuration A
ECP Configuration B
Extended Control Register
Access
ECR 7 5
011
All
All
010
011
110
111
111
All
Read Write
Attribute
RW
RO
RW
RW
RW
RW
RW
RW
RW
NOTES
1 Parallel port base addresses are 278h 378h and 3BCh
2 A register is accessible when the ECR 7 5 field contains the value specified in the ECR 7 5 column The register is not
accessible if the ECR 7 5 field does not match the value specified in this column The term ‘‘All’’ means that the register
is accessible in all modes selected by ECR 7 5
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