82091AA Datasheet, PDF (84/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
6 1 3 8 ECPCFGB ECP Configuration B Register (ECP Mode)
I O Address
Default Value
Attribute
Size
Base ^a401h and (ECR 7 5 ^e111)
00h
Read Write
8 bits
The ECPCFGB Register is part of the ECP specification and is implemented in the 82091AA as a scratchpad
register Software can use the fields in this register to maintain system information Programming these bits
does not affect parallel port operations Access to the ECPCFGB Register is enabled by programming the
ECR Register (ECR 7 5 ^e111)
Figure 37 ECP Extended Control Register (ECP Mode)
290486 – 37
Bit
Description
7 RESERVED This bit always reads back as 0
6 INTRVALUE (INTRV) This bit returns the value on the ISA IRQ line (IRQ5 IRQ7) to determine
possible conflicts The value of either IRQ5 or IRQ7 is read back based on the parallel port interrupt
selection in the 82091AA configuration registers IRQ5 IRQ7 are tri-stated in ECP configuration
mode (ECR 7 5 ^e111 to allow the state of the selected parallel port interrupt line to be read back
Note that the ACKINTEN bit in the PCON register must be written to 0 before the interrupt status can
be read on this bit
5 0 RESERVED These bits always read back as 0
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