82091AA Datasheet, PDF(144/204 Page) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

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82091AA Datasheet, PDF (144/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

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82091AA

Symbol

PCN

PC2 PC1 PC0

PDOSC

PTS

POLL

PRETRK

RCN

SRT

ST0-3

WGATE

Description

PRESENT CYLINDER NUMBER The current position of the head at the completion of

SENSE INTERRUPT STATUS Command

PRECOMPENSATION VALUES Precompensation values from the DSR register

POWERDOWN OSCILLATOR When this bit is set the internal oscillator is turned off

PRECOMPENSATION TABLE SELECT This bit selects whether to enable the precompen-

sation value programmed in the DSR or not In the default state the value programmed in

DSR will be used More information regarding the precompensation is available in Section

815

PTSe0 DSR programmed precompensation delays

PTSe1 No precompensation delay is selected for the corresponding drive

POLLING DISABLE When POLLe1 the internal polling routine is disabled When

POLLe0 polling is enabled

PRECOMPENSATION START TRACK NUMBER Programmable from track 00 to FFh

SECTOR ADDRESS The sector number to be read or written In multi-sector transfers this

parameter specifies the sector number of the first sector to be read or written

RELATIVE CYLINDER NUMBER Relative cylinder offset from present cylinder as used by

the RELATIVE SEEK Command

NUMBER OF SECTORS The number of sectors to be initialized by the FORMAT Command

The number of sectors to be verified during a Verify Command when ECe1

SKIP FLAG When SKe1 sectors containing a deleted data address mark will automatically

be skipped during the execution of a READ DATA Command If a READ DELETED DATA

Command is executed only sectors with a deleted address mark will be accessed When

SKe0 the sector is read or written the same as the read and write commands

STEP RATE INTERVAL The time interval between step pulses issued by the FDC Pro-

grammable from 0 5 ms to 8 ms in increments of 0 5 ms at the 1 Mbit data rate Refer to the

SPECIFY Command for actual delays

STATUS REGISTERS 0-3 Registers within the FDC that store status information after a

command has been executed This status information is available to the host during the

result phase after command execution

WRITE GATE Write gate alters timing of WE to allow for pre-erase loads in perpendicular

drives

8 5 1 STATUS REGISTER ENCODING

The contents of these registers are available only through a command sequence

144

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