82091AA Datasheet, PDF (105/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
Bit
Description
7 6 INTERRUPT TRIGGER LEVEL (ITL) The ITL field indicates the interrupt trigger level When the
number of bytes in the receive FIFO equals the interrupt trigger level programmed into this field and
the Received Data Available Interrupt enabled (via the IER) an interrupt will be generated and the
appropriate bits set in the IIR
Bits 7 6
00
01
10
11
Trigger Level (Bytes)
01 (default)
04
08
14
5 4 RESERVED
3 NOT USED Writing to this bit causes no change in serial port operations The serial port does not
support DMA operations Note that the TXRDY and RXRDY pins are not available in the
82091AA
2 RESET TRANSMITTER FIFO (RESETTF) When RESETTF is set to a 1 the FIFO counter is set to
0 The shift register is not cleared When the FIFO is cleared the 82091AA sets this bit to 0
1 RESET RECEIVER FIFO (RESETRF) When RESETRF is set to a 1 the FIFO counter is set to 0
The shift register is not cleared When the FIFO is cleared the 82091AA sets this bit to 0
0 TRANSMIT AND RECEIVE FIFO ENABLE (TRFIFOE) TRFIFOE enables disables the transmit
and receive FIFOs When TRFIFOE^e1 both FIFOs are enabled (FIFO Mode) When TRFIFOE^e0
the FIFOs are both disabled (non-FIFO MODE) Writing a 0 to this bit clears all bytes in both FIFOs
When changing from FIFO mode to non-FIFO mode and vice versa data is automatically cleared
from the FIFOs This bit must be written with a 1 when other bits in this register are written or the
other bits will not be programmed
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