82091AA Datasheet, PDF (122/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
Bit
Description
7 REQUEST FOR MASTER (RQM) When RQM^e1 the FDC is ready to send receive data through
the FIFO (FDCFIFO Register) The FDC sets this bit to 0 after a byte transfer and then sets the bit to
1 when it is ready for the next byte During non-DMA execution phase RQM indicates the status of
IRQ6
6 DIRECTION I O (DIO) When RQM^e1 DIO indicates the direction of a data transfer When
DIO^e1 the FDC is requesting a read of the FDCFIFO When DIO^e0 the FDC is requesting a write
to the FDCFIFO
5 NON-DMA (NONDMA) Non-DMA mode is selected via the SPECIFY Command In this mode the
FDC sets this bit to a 1 during the execution phase of a command This bit is for polled data
transfers and helps differentiate between the data transfer phase and the reading of result bytes
4 COMMAND BUSY (CMDBUSY) CMDBUSY indicates when a command is in progress When the
first byte of the command phase is written the FDC sets this bit to 1 CMDBUSY is set to 0 after the
last byte of the result phase is read If there is no result phase (e g SEEK or RECALIBRATE
Commands) CMDBUSY is set to 0 after the last command byte is written
3 2 RESERVED For a two-drive system these bits are not used and must be programmed to 0 For a
four drive system see Appendix A FDC Four Drive Support
1 DRIVE 1 BUSY (DRV1BUSY) The FDC module sets this bit to 1 after the last byte of the command
phase of a SEEK or RECALIBRATE Command is issued for drive 1 This bit is set to 0 after the host
reads the first byte in the result phase of the SENSE INTERRUPT Command for this drive
0 DRIVE 0 BUSY (DRV0BUSY) The FDC module sets this bit to 1 after the last byte of the command
phase of a SEEK or RECALIBRATE Command is issued for drive 0 This bit is set to 0 after the host
reads the first byte in the result phase of the SENSE INTERRUPT Command for this drive
8 1 5 DSR DATA RATE SELECT REGISTER
I O Address
Default Value
Attribute
Size
Base ^a4h
02h
Write Only
8 bits
The DSR selects the data rate amount of write precompenstion invokes direct powerdown and invokes a
FDC software reset This write only register ensures backward compatibility with the Intel series of floppy disk
controllers Changing the data rate changes the timings of the drive control signals To ensure that drive
timings are not violated when changing data rates choose a drive timing such that the fastest data rate will not
violate the timing
In the default state the PDOSC bit is low and the oscillator is powered up When this bit is programmed to a 1
the oscillator is shut off Hardware reset sets this bit to a 0 Neither of the software resets (via DOR or DSR)
have any effect on this bit Note that PDOSC should only be set to a 1 when the FDC module is in the
powerdown state Otherwise the FDC will not function correctly and must be hardware reset once the oscilla-
tor has turned back on and stabilized Setting the PDOSC bit has no effect on the clock input to the FDC (the
X1 pin) The clock input is separately disabled when the part is powered down The Save Command checks
the status of PDOSC However the Restore Command will not restore this bit to a 1
Software resets do not affect the DRATE or PRECOMP bits
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