82091AA Datasheet, PDF (75/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
6 1 3 1 ECPAFIFO ECP Address RLE FIFO Register (ECP Mode)
I O Address
Default Value
Attribute
Size
Base ^a00h
UUUU UUUU (Undefined)
Read Write
8 bits
The ECPAFIFO Register provides a channel address or a Run Length Count (RLE) to the peripheral depend-
ing on the state of bit 7 This I O address location is only used in ECP mode (ECR bits 7 5 ^e011) In this
mode bytes written to this register are placed in the parallel port FIFO and transmitted over PD 7 0 using
ECP protocol
NOTE
UeUndefined
290486 – 30
Figure 30 ECP Address RLE FIFO Register (ECP Mode)
Bit
Description
7 0 ECP ADDRESS RLE VALUE Bits 7 0 correspond to parallel port data lines PD 7 0 and ISA Bus
data lines SD 7 0 The peripheral device should interpret bits 6 0 as a channel address when
bit 7^e1 and as a run length count when bit 7^e0 Note that this interpretation is performed by the
peripheral device and the value of bit 7 has no affect on 82091AA operations Note that the
82091AA asserts AUTOFD to indicate that the information on PD 7 0 represents an ECP
address RLE count The 82091AA negates AUTOFD (drives high) when PD 7 0 is transferring
data
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