82091AA Datasheet, PDF (24/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
2 6 4 ENHANCED PARALLEL PORT (EPP) PROTOCOL SIGNAL DESCRIPTION
EPP protocol assigns the following signal operation to the parallel port pins The name in bold at the beginning
of the signal description column is the EPP mode signal name The terms assert and negate are used in
accordance with the 82091AA signal name as described at the beginning of Section 2 0 For example BUSY
(Wait ) asserted refers to BUSY (Wait ) being high
82091AA
Signal Name
STROBE
BUSY
ACK
SELECT
PERROR
FAULT
INIT
AUTOFD
PD 7 0
SELECTIN
Type
O
I
I
I
I
I
O
O
IO
O
EPP Protocol Signal Name and Description
WRITE (Write ) STROBE (Write ) indicates an address or data read write
operation to the peripheral The 82091AA drives this signal low for a write and
high for a read
WAIT (Wait ) The peripheral sets BUSY (Wait ) low to indicate that the device
is not ready When BUSY signal is low the 82091AA negates IOCHRDY on the
ISA Bus to lengthen the I O cycles The peripheral device sets BUSY (Wait )
high to indicate that transfer of data or address is completed
INTERRUPT REQUEST (Intr) The peripheral asserts ACK (Intr) to generate
an interrupt the host When this signal is low and interrupts are enabled via bit 4
of the PCON Register the 82091AA generates an interrupt request (via either
IRQ5 or IRQ7) to the host
SELECT SELECT is asserted by the peripheral device to indicate that the
device is on line The status of this signal line is reported in the PSTAT Register
PAPER ERROR The peripheral device asserts PERROR to indicate that it has
encountered an error in the paper path The exact meaning varies from
peripheral device to peripheral device The status of this signal line is reported in
the PSTAT Register
FAULT FAULT is asserted by the peripheral device to indicate that an error
has occurred The status of this signal line is reported in the PSTAT Register
INITIALIZE The host asserts INIT to issue a hardware reset to the peripheral
device This signal is controlled via the PCON Register
DATA STROBE (DStrb ) The 82091AA asserts AUTOFD (DStrb ) to
indicate that valid data is present on PD 7 0 and is used by the peripheral to
latch data during write cycles For reads the 82091AA reads in data from
PD 7 0 when this signal is asserted
DATA This 8-bit bi-directional bus provides addresses or data during the write
cycles and supplies addresses or data to the 82091AA during the read cycles
ADDRESS STROBE (AStrb ) The 82091AA asserts SELECTIN (AStrb ) to
indicate that a valid address is present on PD 7 0 and is used by the peripheral
to latch addresses during write cycles For reads the 82091AA reads in an
address from PD 7 0 when this signal is asserted
2 6 5 EXTENDED CAPABILITIES PORT (ECP) PROTOCOL SIGNAL DESCRIPTION
ECP protocol assigns the following signal operation to the parallel port pins The name in bold at the beginning
of the signal description column is the ECP protocol signal name The terms assert and negate are used in
accordance with the 82091AA signal name as described at the beginning of Section 2 0 For example
STROBE (HostClk) asserted refers to STROBE (HostClk) being low
24