82091AA Datasheet, PDF (87/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
Bit
Description
4 ERROR INTERRUPT DISABLE (ERRINTREN) This bit enables error interrupts to the host In ECP
Mode When ERRINTREN^e1 interrupts are disabled When ERRINTREN^e0 interrupts are
enabled When enabled and a high-to-low transition occurs on the FAULT signal (FAULT
asserted) an interrupt is generated to the host Note that if this bit is written from a 1 to a 0 while
FAULT is asserted an interrupt is generated to the host
3 DMA ENABLE (DMAEN) This bit enables disables DMA When DMAEN^e1 DMA is enabled and
the host uses PPDREQ PPDACK and TC to transfer data When DMAEN^e0 DMA is disabled and
the PPDREQ output is tri-stated In this case programmed I O is used to transfer data between the
host and the 82091AA FIFO The Service Interrupt (bit 2) needs to be set to 0 to allow generation of
a TC interrupt This bit must be written to 0 to reset the TC interrupt
2 SERVICE INTERRUPT (SERVICEINTR) This bit enables FIFO and TC service interrupts When the
CPU writes SERVICEINTR^e1 FIFO request interrupts FIFO error interrupts and TC interrupts are
disabled Setting this bit to a 0 enables interrupts for one of the four cases listed below When
enabled (set to 0) and one of the four conditions below occurs the 82091AA sets SERVICEINTR to
a 1 and generates an interrupt to the host
1 During DMA operations (DMAEN^e1) when terminal count is reached (TC asserted) To clear the
TC interrupt switch to ISA-Compatible or PS 2-Compatible mode (write ECR 7 5 to 000 001) or
set DMAEN to 0
2 In the forward direction and DMAEN^e0 when there is a threshold number of bytes in the FIFO to
be written
3 In the reverse direction and DMAEN^e0 when there is a threshold number of bytes in the FIFO to
be read
4 In either DMA or programmed I O mode when there is a FIFO overrun or underrun
Reading the SERVICEINTR bit indicates the presence of an active interrupt when this bit has been
written to a 0 prior to reading it back To disable interrupts the SERVICEINTR bit must be explicitly
written to a 1
NOTE
The ACK and FAULT interrupts can be generated independent of the value of the
SERVICEINTR bit ACK and FAULT interrupts are enabled via the ACKINTREN bit in the PCON
Register and the ERRINTREN bit in the ECR Registers respectively The parallel port IRQ output
(IRQ5 IRQ7) is enabled when ACKINTREN^e1 in the PCON Register or when ECR 7 5 ^e010 011
or 110 Otherwise the IRQ output is tri-stated
1 FIFO FULL STATUS (FIFOFS) This bit indicates when the FIFO is full When FIFOFS^e1 (and
FIFOES^e0) the FIFO is full and cannot accept another byte of data When FIFOFS^e0 at least one
byte location is free in the FIFO This bit is read only and writes have no affect When a FIFO overrun
or underrun occurs the 82091AA sets both FIFOES and FIFOFS to 1 To clear the FIFO error
condition interrupt swiitch the parallel port mode from ECP (011) to either ISA-Compatible or PS 2-
Compatible modes (000 or 001)
0 FIFO EMPTY STATUS (FIFOES) This bit indicates when the FIFO is empty When FIFOES^e1 (and
FIFOFS^e0) the FIFO is empty When FIFOES^e0 the FIFO contains at least one byte This bit is
read only and writes have no affect When a FIFO overrun or underrun occurs the 82091AA sets
both FIFOES and FIFOFS to 1 To clear the FIFO error condition interrupt swiitch the parallel port
mode from ECP (011) to either ISA-Compatible or PS 2-Compatible modes (000 or 001)
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