82091AA Datasheet, PDF (164/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

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82091AA
down again after being idle for the time specified by
MIN DLY) However the FDC does not remain in
auto powerdown mode after a hardware reset or
DSR reset
Direct Powerdown
Direct powerdown is invoked via the Powerdown bit
in the Data Rate Select Register (bit 6) or the
FDPDN bit in the FCFG2 Register Setting FDPDN
to 1 will powerdown the FDC All status is lost when
this type of powerdown mode is used The FDC exits
powerdown mode after any hardware or software re-
set Direct powerdown overrides automatic power-
down
Recovery from Direct Powerdown
The FDC exits the direct powerdown state by setting
the FDPDN bit to 0 followed by a software or hard-
ware reset
After reset the FDC goes through a normal se-
quence The drive status is initialized The FIFO
mode is set to default mode on a hardware or soft-
ware reset if the LOCK Command has not blocked it
Finally after a delay the polling interrupt is issued
10 4 Serial Port Power Management
This section describes the serial port direct and auto
powerdown modes and recovery from the power-
down modes
Auto Powerdown
When auto powerdown is enabled in the SxCFG2
Register (SxAPDN bit is 1) the serial port enters
auto powerdown based on monitoring line interface
activity During auto powerdown the status of the
serial port is maintained (the FIFO and registers are
not reset) Access to any serial port register is al-
lowed during auto powerdown The transmitter and
the receiver enter powerdown individually depend-
ing on certain conditions When there are no charac-
ters to transmit (TEMPTY^e1 in the LSR) the trans-
mitter clock is shut off placing the transmitter in auto
powerdown In the case of the receiver when serial
input signal is inactive for approximately 5 character
times indicating that no character is being received
the receiver goes into auto powerdown
Recovery from Auto Powerdown
The serial port recovers from auto powerdown when
either the transmitter or receiver are active If data is
written to the transmitter or data is present at the
receiver the serial port exits from auto powerdown
Direct Powerdown
Direct Powerdown is invoked via the SxCFG2 Regis-
ter (setting the SxDPDN bit to 1) When in direct
powerdown the clock to the module is shut off All
registers are accessible while in direct powerdown
A host read of the Receiver Buffer Register or a
write to the Transmitter Holding Register should not
be performed during powerdown The SINx input
should remain static
When direct powerdown is invoked the transmit and
receive sections of the serial port are reset includ-
ing the transmit and receive FIFOs Thus to prevent
possible data loss when the FIFOs are reset soft-
ware should not invoke direct powerdown until the
serial port is in the idle state as indicated by the
SxIDLE bit in the SxCFG2 Register
Recovery from Direct Powerdown
Recovery from direct powerdown is accomplished
by writing the SxDPDN bit in the configuration regis-
ter to 0 or by a module reset
10 5 Parallel Port Power Management
Auto Powerdown
Auto powerdown is enabled via the PAPDN bit in the
PCFG2 Register When enabled the parallel port
enters auto powerdown when the module is in an
idle state If the parallel port FIFO is being used to
transfer data the parallel port is in an idle state
when the FIFO is empty
Recovery from Auto Powerdown
Recovery from auto powerdown occurs when the
FIFO is written or as a result of parallel port interface
activity
Direct Powerdown
Direct powerdown is invoked via the PCFG2 Regis-
ter (setting the PDPDN bit to 1) When PDPDN^e1
the clock to the printer state machine is disabled
and the state machine goes into an idle state
Recovery from Direct Powerdown
Recovery from direct powerdown is accomplished
by setting the PDPDN bit to 0 or the PRESET bit to a
1 in the PCFG2 Register An 82091AA hard reset
(RSTDRV asserted) also brings the part out of direct
powerdown
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